mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-27 23:35:10 +00:00
75fbf5546b
Adds bl2 with FIP to the build required for mbed Linux booting where we do: BootROM -> SPL -> BL2 -> OPTEE -> u-boot If NEED_BL2 is specified then BL2 will be built and BL31 will have its address range modified upwards to accommodate. BL31 must be loaded from a FIP in this case. If NEED_BL2 is not specified then the current BL31 boot flow is unaffected and u-boot SPL will load and execute BL31 directly. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I78914d6002755f733ea866127cb47982a00f9700
117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/mmc.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <imx8m_caam.h>
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#include "imx8mp_private.h"
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#include <imx_aipstz.h>
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#include <imx_rdc.h>
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#include <imx_uart.h>
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#include <plat/common/platform.h>
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#include <plat_imx8.h>
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#include <platform_def.h>
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static const struct aipstz_cfg aipstz[] = {
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{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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unsigned int i;
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/* Enable CSU NS access permission */
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for (i = 0U; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
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}
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imx_aipstz_init(aipstz);
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console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
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/* Open handles to a FIP image */
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plat_imx_io_setup();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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void bl2_platform_setup(void)
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{
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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void bl2_plat_runtime_setup(void)
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{
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return;
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}
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