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https://github.com/ARM-software/arm-trusted-firmware.git
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ae6ce196df
The i.MX8MP exists in multiple SKUs, some of which lack the NPU or VPU.
Yet, we unconditionally enable NPU and VPU power domains in upstream
TF-A, causing it to hang on such SoCs, unless patched.
Enabling all power domains is an idiosyncrasy of the i.MX8MP support,
which we don't have on i.MX8MQ, i.MX8MM or i.MX8MN. Therefore let's drop
unconditional powering on of all power domains.
As only exception, we will keep enabling the USB power domains. These
are enabled in the BootROM if booting over SDPS and boot firmware may
expect them to be enabled for non-SDPS recovery too. As USB is
available unconditionally on the current i.MX8MP variants, this is
deemed acceptable and reduces the chance of breaking existing systems.
Fixes: a775ef25c3 ("plat: imx8mp: Add the basic support for i.MX8MP")
Change-Id: Idc6e8f770d240f4d929dffa91f9ccf8c476c6c12
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* Copyright 2019-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <lib/smccc.h>
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#include <services/std_svc.h>
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#include <gpc.h>
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#include <imx_aipstz.h>
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#include <imx_sip_svc.h>
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#include <platform_def.h>
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#define CCGR(x) (0x4000 + (x) * 0x10)
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#define IMR_NUM U(5)
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struct imx_noc_setting {
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uint32_t domain_id;
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uint32_t start;
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uint32_t end;
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uint32_t prioriy;
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uint32_t mode;
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uint32_t socket_qos_en;
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};
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enum clk_type {
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CCM_ROOT_SLICE,
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CCM_CCGR,
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};
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struct clk_setting {
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uint32_t offset;
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uint32_t val;
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enum clk_type type;
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};
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enum pu_domain_id {
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/* hsio ss */
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HSIOMIX,
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PCIE_PHY,
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USB1_PHY,
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USB2_PHY,
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MLMIX,
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AUDIOMIX,
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/* gpu ss */
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GPUMIX,
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GPU2D,
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GPU3D,
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/* vpu ss */
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VPUMIX,
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VPU_G1,
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VPU_G2,
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VPU_H1,
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/* media ss */
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MEDIAMIX,
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MEDIAMIX_ISPDWP,
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MIPI_PHY1,
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MIPI_PHY2,
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/* HDMI ss */
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HDMIMIX,
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HDMI_PHY,
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DDRMIX,
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MAX_DOMAINS,
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};
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/* PU domain, add some hole to minimize the uboot change */
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static struct imx_pwr_domain pu_domains[MAX_DOMAINS] = {
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[MIPI_PHY1] = IMX_PD_DOMAIN(MIPI_PHY1, false),
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[PCIE_PHY] = IMX_PD_DOMAIN(PCIE_PHY, false),
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[USB1_PHY] = IMX_PD_DOMAIN(USB1_PHY, true),
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[USB2_PHY] = IMX_PD_DOMAIN(USB2_PHY, true),
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[MLMIX] = IMX_MIX_DOMAIN(MLMIX, false),
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[AUDIOMIX] = IMX_MIX_DOMAIN(AUDIOMIX, false),
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[GPU2D] = IMX_PD_DOMAIN(GPU2D, false),
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[GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false),
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[VPUMIX] = IMX_MIX_DOMAIN(VPUMIX, false),
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[GPU3D] = IMX_PD_DOMAIN(GPU3D, false),
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[MEDIAMIX] = IMX_MIX_DOMAIN(MEDIAMIX, false),
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[VPU_G1] = IMX_PD_DOMAIN(VPU_G1, false),
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[VPU_G2] = IMX_PD_DOMAIN(VPU_G2, false),
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[VPU_H1] = IMX_PD_DOMAIN(VPU_H1, false),
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[HDMIMIX] = IMX_MIX_DOMAIN(HDMIMIX, false),
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[HDMI_PHY] = IMX_PD_DOMAIN(HDMI_PHY, false),
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[MIPI_PHY2] = IMX_PD_DOMAIN(MIPI_PHY2, false),
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[HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false),
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[MEDIAMIX_ISPDWP] = IMX_PD_DOMAIN(MEDIAMIX_ISPDWP, false),
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};
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static struct imx_noc_setting noc_setting[] = {
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{MLMIX, 0x180, 0x180, 0x80000303, 0x0, 0x0},
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{AUDIOMIX, 0x200, 0x200, 0x80000303, 0x0, 0x0},
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{AUDIOMIX, 0x280, 0x480, 0x80000404, 0x0, 0x0},
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{GPUMIX, 0x500, 0x580, 0x80000303, 0x0, 0x0},
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{HDMIMIX, 0x600, 0x680, 0x80000202, 0x0, 0x1},
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{HDMIMIX, 0x700, 0x700, 0x80000505, 0x0, 0x0},
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{HSIOMIX, 0x780, 0x900, 0x80000303, 0x0, 0x0},
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{MEDIAMIX, 0x980, 0xb80, 0x80000202, 0x0, 0x1},
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{MEDIAMIX_ISPDWP, 0xc00, 0xd00, 0x80000505, 0x0, 0x0},
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{VPU_G1, 0xd80, 0xd80, 0x80000303, 0x0, 0x0},
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{VPU_G2, 0xe00, 0xe00, 0x80000303, 0x0, 0x0},
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{VPU_H1, 0xe80, 0xe80, 0x80000303, 0x0, 0x0}
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};
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static struct clk_setting hsiomix_clk[] = {
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{ 0x8380, 0x0, CCM_ROOT_SLICE },
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{ 0x44d0, 0x0, CCM_CCGR },
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{ 0x45c0, 0x0, CCM_CCGR },
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};
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static struct aipstz_cfg aipstz5[] = {
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{IMX_AIPSTZ5, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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static unsigned int pu_domain_status;
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static void imx_noc_qos(unsigned int domain_id)
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{
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unsigned int i;
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uint32_t hurry;
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if (domain_id == HDMIMIX) {
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mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018);
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mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010);
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/* set GPR to make lcdif read hurry level 0x7 */
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hurry = mmio_read_32(IMX_HDMI_CTL_BASE + TX_CONTROL0);
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hurry |= 0x00077000;
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mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry);
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}
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if (domain_id == MEDIAMIX) {
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/* handle mediamix special */
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mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RSTn_CSR, 0x1FFFFFF);
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mmio_write_32(IMX_MEDIAMIX_CTL_BASE + CLK_EN_CSR, 0x1FFFFFF);
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mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RST_DIV, 0x40030000);
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/* set GPR to make lcdif read hurry level 0x7 */
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hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL);
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hurry |= 0xfc00;
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mmio_write_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL, hurry);
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/* set GPR to make isi write hurry level 0x7 */
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hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL);
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hurry |= 0x1ff00000;
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mmio_write_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL, hurry);
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}
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/* set MIX NoC */
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for (i = 0; i < ARRAY_SIZE(noc_setting); i++) {
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if (noc_setting[i].domain_id == domain_id) {
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udelay(50);
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uint32_t offset = noc_setting[i].start;
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while (offset <= noc_setting[i].end) {
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mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy);
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mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode);
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mmio_write_32(IMX_NOC_BASE + offset + 0x18, noc_setting[i].socket_qos_en);
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offset += 0x80;
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}
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}
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}
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}
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void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
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{
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struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
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unsigned int i;
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/* validate the domain id */
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if (domain_id >= MAX_DOMAINS) {
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return;
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}
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if (domain_id == HSIOMIX) {
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for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
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hsiomix_clk[i].val = mmio_read_32(IMX_CCM_BASE + hsiomix_clk[i].offset);
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mmio_setbits_32(IMX_CCM_BASE + hsiomix_clk[i].offset,
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hsiomix_clk[i].type == CCM_ROOT_SLICE ? BIT(28) : 0x3);
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}
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}
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if (on) {
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if (pwr_domain->need_sync) {
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pu_domain_status |= (1 << domain_id);
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}
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if (domain_id == HDMIMIX) {
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/* assert the reset */
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0);
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/* enable all th function clock */
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
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}
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/* clear the PGC bit */
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mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
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/* power up the domain */
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req)
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;
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if (domain_id == HDMIMIX) {
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/* wait for memory repair done for HDMIMIX */
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while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8)))
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;
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/* disable all the function clock */
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0);
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0);
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/* deassert the reset */
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff);
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/* enable all the clock again */
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
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mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
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}
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if (domain_id == HSIOMIX) {
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/* enable HSIOMIX clock */
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mmio_write_32(IMX_HSIOMIX_CTL_BASE, 0x2);
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}
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/* handle the ADB400 sync */
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if (pwr_domain->need_sync) {
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/* clear adb power down request */
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mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
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/* wait for adb power request ack */
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while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
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;
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}
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imx_noc_qos(domain_id);
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/* AIPS5 config is lost when audiomix is off, so need to re-init it */
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if (domain_id == AUDIOMIX) {
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imx_aipstz_init(aipstz5);
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}
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} else {
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if (pwr_domain->always_on) {
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return;
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}
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if (pwr_domain->need_sync) {
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pu_domain_status &= ~(1 << domain_id);
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}
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/* handle the ADB400 sync */
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if (pwr_domain->need_sync) {
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/* set adb power down request */
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mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
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/* wait for adb power request ack */
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while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
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;
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}
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/* set the PGC bit */
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mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
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/*
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* leave the G1, G2, H1 power domain on until VPUMIX power off,
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* otherwise system will hang due to VPUMIX ACK
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*/
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if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
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return;
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}
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if (domain_id == VPUMIX) {
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mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
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VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
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VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
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;
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}
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/* power down the domain */
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req)
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;
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if (domain_id == HDMIMIX) {
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/* disable all the clocks of HDMIMIX */
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mmio_write_32(IMX_HDMI_CTL_BASE + 0x40, 0x0);
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mmio_write_32(IMX_HDMI_CTL_BASE + 0x50, 0x0);
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}
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}
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if (domain_id == HSIOMIX) {
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for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
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mmio_write_32(IMX_CCM_BASE + hsiomix_clk[i].offset, hsiomix_clk[i].val);
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}
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}
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}
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void imx_gpc_init(void)
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{
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uint32_t val;
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unsigned int i;
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/* mask all the wakeup irq by default */
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for (i = 0; i < IMR_NUM; i++) {
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
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}
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val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
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/* use GIC wake_request to wakeup C0~C3 from LPM */
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val |= CORE_WKUP_FROM_GIC;
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/* clear the MASTER0 LPM handshake */
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val &= ~MASTER0_LPM_HSK;
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mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
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/* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
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mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
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MASTER2_MAPPING));
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/* set all mix/PU in A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0x3fffff);
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/*
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* Set the CORE & SCU power up timing:
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* SW = 0x1, SW2ISO = 0x1;
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* the CPU CORE and SCU power up timing counter
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* is drived by 32K OSC, each domain's power up
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* latency is (SW + SW2ISO) / 32768
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*/
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
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(0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT));
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/* set DUMMY PDN/PUP ACK by default for A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
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A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
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/* clear DSM by default */
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val = mmio_read_32(IMX_GPC_BASE + SLPCR);
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val &= ~SLPCR_EN_DSM;
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/* enable the fast wakeup wait/stop mode */
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val |= SLPCR_A53_FASTWUP_WAIT_MODE;
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val |= SLPCR_A53_FASTWUP_STOP_MODE;
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/* clear the RBC */
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val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
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/* set the STBY_COUNT to 0x5, (128 * 30)us */
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val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
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val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
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mmio_write_32(IMX_GPC_BASE + SLPCR, val);
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/*
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* USB PHY power up needs to make sure RESET bit in SRC is clear,
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* otherwise, the PU power up bit in GPC will NOT self-cleared.
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* only need to do it once.
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*/
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
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/* enable all clocks by default */
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for (i = 0; i < 101; i++) {
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mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3);
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}
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/* Depending on SKU, we may be lacking e.g. a VPU and shouldn't
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* access that domain here, because that would lockup the SoC.
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* Other i.MX8M variants don't initialize any power domains, but
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* for 8MP we have been enabling the USB power domains since the
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* beginning and stopping to do this now may render systems
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* unrecoverable. So we'll keep initializing just the USB power
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* domains instead of all of them like before.
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*/
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imx_gpc_pm_domain_enable(HSIOMIX, true);
|
|
imx_gpc_pm_domain_enable(USB1_PHY, true);
|
|
imx_gpc_pm_domain_enable(USB2_PHY, true);
|
|
}
|