mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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81d1d86c89
This commit makes imx image io-storage logic common for all imx platform. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I15045ac8f9dfa8cb714e32f9e7475d5eae4e86e4
143 lines
3.5 KiB
C
143 lines
3.5 KiB
C
/*
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* Copyright 2017-2021 NXP
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* Copyright 2021 Arm
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <context.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/mmc.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/utils.h>
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#include <stdbool.h>
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#include <tbbr_img_def.h>
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#include <imx_aipstz.h>
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#include <imx_csu.h>
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#include <imx_uart.h>
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#include <imx_usdhc.h>
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#include <plat/common/platform.h>
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#include "imx8mm_private.h"
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#include "platform_def.h"
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static const struct aipstz_cfg aipstz[] = {
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{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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static void imx8mm_usdhc_setup(void)
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{
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imx_usdhc_params_t params;
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struct mmc_device_info info;
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params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
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/*
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The imx8mm SD Card Speed modes for USDHC2
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+--------------+--------------------+--------------+--------------+
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|Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
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+--------------+--------------------+--------------+--------------+
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|Default Speed | 25 MHz | 12.5 MB/s | 3.3V |
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|High Speed | 50 MHz | 25 MB/s | 3.3V |
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+--------------+--------------------+--------------+--------------+
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We pick 50 Mhz here for High Speed access.
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*/
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params.clk_rate = 50000000;
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params.bus_width = MMC_BUS_WIDTH_1;
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params.flags = 0;
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info.mmc_dev_type = MMC_IS_SD;
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info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
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imx_usdhc_init(¶ms, &info);
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}
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void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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int i;
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static console_t console;
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/* enable CSU NS access permission */
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for (i = 0; i < MAX_CSU_NUM; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
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}
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/* config the aips access permission */
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imx_aipstz_init(aipstz);
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console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(0x30360124, 0x1);
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imx8mm_usdhc_setup();
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/* Open handles to a FIP image */
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plat_imx_io_setup();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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void bl2_platform_setup(void)
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{
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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void bl2_plat_runtime_setup(void)
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{
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return;
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}
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