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arm-trusted-firmware/plat/imx/common/sci/svc/timer
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Anson Huang 1552df5d25 Support for NXP's i.MX8 SoCs timer IPC 
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.

This patch adds timer IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-17 10:49:48 +08:00
..
sci_timer_rpc.h Support for NXP's i.MX8 SoCs timer IPC 2019-01-17 10:49:48 +08:00
timer_rpc_clnt.c Support for NXP's i.MX8 SoCs timer IPC 2019-01-17 10:49:48 +08:00