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https://github.com/ARM-software/arm-trusted-firmware.git
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dc5baeb3c2
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
36 lines
1 KiB
C
36 lines
1 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#define MU_ATR0_OFFSET1 0x0
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#define MU_ARR0_OFFSET1 0x10
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#define MU_ASR_OFFSET1 0x20
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#define MU_ACR_OFFSET1 0x24
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#define MU_TR_COUNT1 4
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#define MU_RR_COUNT1 4
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#define MU_CR_GIEn_MASK1 (0xFu << 28)
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#define MU_CR_RIEn_MASK1 (0xF << 24)
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#define MU_CR_TIEn_MASK1 (0xF << 20)
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#define MU_CR_GIRn_MASK1 (0xF << 16)
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#define MU_CR_NMI_MASK1 (1 << 3)
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#define MU_CR_Fn_MASK1 0x7
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#define MU_SR_TE0_MASK1 (1 << 23)
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#define MU_SR_RF0_MASK1 (1 << 27)
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#define MU_CR_RIE0_MASK1 (1 << 27)
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#define MU_CR_GIE0_MASK1 (1U << 31)
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#define MU_TR_COUNT 4
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#define MU_RR_COUNT 4
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void MU_Init(uint32_t base);
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void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
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void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
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void MU_EnableGeneralInt(uint32_t base, uint32_t index);
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void MU_EnableRxFullInt(uint32_t base, uint32_t index);
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void MU_Resume(uint32_t base);
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