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3a2b51993d
Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include "imx8_mu.h"
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void MU_Resume(uint32_t base)
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{
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uint32_t reg, i;
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reg = mmio_read_32(base + MU_ACR_OFFSET1);
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/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
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reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
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| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
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mmio_write_32(base + MU_ACR_OFFSET1, reg);
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/* Enable all RX interrupts */
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for (i = 0; i < MU_RR_COUNT; i++)
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MU_EnableRxFullInt(base, i);
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}
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void MU_EnableRxFullInt(uint32_t base, uint32_t index)
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{
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uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
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reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
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reg |= MU_CR_RIE0_MASK1 >> index;
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mmio_write_32(base + MU_ACR_OFFSET1, reg);
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}
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void MU_EnableGeneralInt(uint32_t base, uint32_t index)
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{
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uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
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reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
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reg |= MU_CR_GIE0_MASK1 >> index;
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mmio_write_32(base + MU_ACR_OFFSET1, reg);
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}
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void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
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{
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uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
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/* Wait TX register to be empty. */
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while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
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;
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mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
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}
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void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
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{
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uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
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/* Wait RX register to be full. */
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while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
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;
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*msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
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}
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void MU_Init(uint32_t base)
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{
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uint32_t reg;
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reg = mmio_read_32(base + MU_ACR_OFFSET1);
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/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
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reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
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| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
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mmio_write_32(base + MU_ACR_OFFSET1, reg);
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}
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