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535c824e38
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I397b642eff8a09b201f497f8d2ba39e2460c0dba
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include "fpga_private.h"
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#include <platform_def.h>
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/*
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* This is a basic PSCI implementation that allows secondary CPUs to be
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* released from their initial state and continue to the warm boot entrypoint.
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*
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* The secondary CPUs are placed in a holding pen and released by calls
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* to fpga_pwr_domain_on(mpidr), which updates the hold entry for the CPU
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* specified by the mpidr argument - the (polling) target CPU will then branch
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* to the BL31 warm boot sequence at the entrypoint address.
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*
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* Additionally, the secondary CPUs are kept in a low-power wfe() state
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* (placed there at the end of each poll) and woken when necessary through
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* calls to sev() in fpga_pwr_domain_on(mpidr), once the hold state for the
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* relevant CPU has been updated.
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*
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* Hotplug is currently implemented using a wfi-loop, which removes the
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* dependencies on any power controllers or other mechanism that is specific
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* to the running system as specified by the FPGA image.
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*/
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uint64_t hold_base[PLATFORM_CORE_COUNT];
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uintptr_t fpga_sec_entrypoint;
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/*
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* Calls to the CPU specified by the mpidr will set its hold entry to a value
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* indicating that it should stop polling and branch off to the warm entrypoint.
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*/
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static int fpga_pwr_domain_on(u_register_t mpidr)
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{
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int pos = plat_core_pos_by_mpidr(mpidr);
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unsigned long current_mpidr = read_mpidr_el1();
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if (pos < 0) {
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panic();
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}
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if (mpidr == current_mpidr) {
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return PSCI_E_ALREADY_ON;
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}
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hold_base[pos] = PLAT_FPGA_HOLD_STATE_GO;
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flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t));
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sev(); /* Wake any CPUs from wfe */
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return PSCI_E_SUCCESS;
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}
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void fpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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fpga_pwr_gic_on_finish();
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}
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static void fpga_pwr_domain_off(const psci_power_state_t *target_state)
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{
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fpga_pwr_gic_off();
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while (1) {
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wfi();
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}
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}
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static void fpga_cpu_standby(plat_local_state_t cpu_state)
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{
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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u_register_t scr = read_scr_el3();
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write_scr_el3(scr|SCR_IRQ_BIT);
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dsb();
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wfi();
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write_scr_el3(scr);
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}
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plat_psci_ops_t plat_fpga_psci_pm_ops = {
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.pwr_domain_on = fpga_pwr_domain_on,
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.pwr_domain_on_finish = fpga_pwr_domain_on_finish,
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.pwr_domain_off = fpga_pwr_domain_off,
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.cpu_standby = fpga_cpu_standby
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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fpga_sec_entrypoint = sec_entrypoint;
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flush_dcache_range((uint64_t)&fpga_sec_entrypoint,
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sizeof(fpga_sec_entrypoint));
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*psci_ops = &plat_fpga_psci_pm_ops;
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return 0;
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}
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