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da04341ed5
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
53 lines
1.1 KiB
ArmAsm
53 lines
1.1 KiB
ArmAsm
/*
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* Copyright (c) 2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Linker script for the Arm Ltd. FPGA boards to generate an ELF file that
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* contains the ROM trampoline, BL31 and the DTB.
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*
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* This allows to pass just one file to the uploader tool, and automatically
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* provides the correct load addresses.
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*/
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#include <platform_def.h>
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OUTPUT_FORMAT("elf64-littleaarch64")
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OUTPUT_ARCH(aarch64)
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INPUT(./rom_trampoline.o)
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INPUT(./kernel_trampoline.o)
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TARGET(binary)
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INPUT(./bl31.bin)
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INPUT(./fdts/arm_fpga.dtb)
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ENTRY(_start)
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SECTIONS
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{
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.rom (0x0): {
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*rom_trampoline.o(.text*)
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KEEP(*(.rom))
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}
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.bl31 (BL31_BASE): {
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ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE is not page aligned");
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*bl31.bin
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}
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.dtb (FPGA_PRELOADED_DTB_BASE): {
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ASSERT(. == ALIGN(8), "DTB address is not 8-byte aligned");
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*arm_fpga.dtb
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}
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.kern_tramp (PRELOADED_BL33_BASE): {
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*kernel_trampoline.o(.text*)
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KEEP(*(.kern_tramp))
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}
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/DISCARD/ : { *(.stacks) }
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/DISCARD/ : { *(.debug_*) }
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/DISCARD/ : { *(.note*) }
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/DISCARD/ : { *(.comment*) }
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}
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