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c20c05252c
The SCU connects one to four Cortex-A5/Cortex-A9 processors to the memory system through the AXI interfaces. The SCU functions are to: - maintain data cache coherency between the Cortex-A5/Cortex-A9 processors - initiate L2 AXI memory accesses - arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses - manage ACP accesses. Snoop Control Unit will enable to snoop on other CPUs caches. This is very important when it comes to synchronizing data between CPUs. As an example, there is a high chance that data might be cache'd and other CPUs can't see the change. In such cases, if snoop control unit is enabled, data is synchoronized immediately between CPUs and the changes are visible to other CPUs. This driver provides functionality to enable SCU as well as enabling user to know the following - number of CPUs present - is a particular CPU operating in SMP mode or AMP mode - data cache size of a particular CPU - does SCU has ACP port - is L2CPRESENT Change-Id: I0d977970154fa60df57caf449200d471f02312a0 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
75 lines
2.6 KiB
C
75 lines
2.6 KiB
C
/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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static int a5ds_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int pos = plat_core_pos_by_mpidr(mpidr);
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uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE;
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hold_base[pos] = A5DS_HOLD_STATE_GO;
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dsbish();
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sev();
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/* TODO: This setup is needed only after a cold boot*/
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gicv2_pcpu_distif_init();
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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* a5ds only has always-on power domain and there is no power control present.
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******************************************************************************/
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void a5ds_pwr_domain_off(const psci_power_state_t *target_state)
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{
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ERROR("CPU_OFF not supported on this platform\n");
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assert(false);
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panic();
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}
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/*******************************************************************************
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* Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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plat_psci_ops_t a5ds_psci_pm_ops = {
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/* dummy struct */
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.validate_ns_entrypoint = NULL,
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.pwr_domain_on = a5ds_pwr_domain_on,
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.pwr_domain_on_finish = a5ds_pwr_domain_on_finish,
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.pwr_domain_off = a5ds_pwr_domain_off
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};
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int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE;
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*mailbox = sec_entrypoint;
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*psci_ops = &a5ds_psci_pm_ops;
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return 0;
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}
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