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f2bd352820
Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and is still open. Under some conditions, data might be corrupted if Trace Buffer Extension (TRBE) is enabled. The workaround is to disable trace collection via TRBE by programming MDCR_EL3.NSTB[1] to the opposite value of SCR_EL3.NS on a security state switch. Since we only enable TRBE for non-secure world, the workaround is to disable TRBE by setting the NSTB field to 00 so accesses are trapped to EL3 and secure state owns the buffer. SDEN: https://developer.arm.com/documentation/SDEN-1873361/latest/ Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ia77051f6b64c726a8c50596c78f220d323ab7d97
153 lines
3.9 KiB
C
153 lines
3.9 KiB
C
/*
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Runtime C routines for errata workarounds and common routines */
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#include <arch.h>
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#include <arch_helpers.h>
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#include <cortex_a75.h>
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#include <cortex_a510.h>
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#include <cortex_a520.h>
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#include <cortex_a710.h>
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#include <cortex_a715.h>
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#include <cortex_a720.h>
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#include <cortex_a720_ae.h>
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#include <cortex_a725.h>
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#include <cortex_x2.h>
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#include <cortex_x3.h>
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#include <cortex_x4.h>
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#include <cortex_x925.h>
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#include <lib/cpus/cpu_ops.h>
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#include <lib/cpus/errata.h>
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#include <neoverse_n2.h>
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#include <neoverse_n3.h>
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#include <neoverse_v3.h>
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bool check_if_trbe_disable_affected_core(void)
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{
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switch (EXTRACT_PARTNUM(read_midr())) {
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#if ERRATA_A520_2938996
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case EXTRACT_PARTNUM(CORTEX_A520_MIDR):
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return check_erratum_cortex_a520_2938996(cpu_get_rev_var()) == ERRATA_APPLIES;
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#endif
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#if ERRATA_X4_2726228
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case EXTRACT_PARTNUM(CORTEX_X4_MIDR):
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return check_erratum_cortex_x4_2726228(cpu_get_rev_var()) == ERRATA_APPLIES;
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#endif
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#if ERRATA_A510_2971420
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case EXTRACT_PARTNUM(CORTEX_A510_MIDR):
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return check_erratum_cortex_a510_2971420(cpu_get_rev_var()) == ERRATA_APPLIES;
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#endif
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default:
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break;
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}
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return false;
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}
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#if ERRATA_A75_764081
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bool errata_a75_764081_applies(void)
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{
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long rev_var = cpu_get_rev_var();
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if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
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return true;
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}
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return false;
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}
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#endif /* ERRATA_A75_764081 */
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bool errata_ich_vmcr_el2_applies(void)
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{
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switch (EXTRACT_PARTNUM(read_midr())) {
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#if ERRATA_A710_3701772
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case EXTRACT_PARTNUM(CORTEX_A710_MIDR):
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if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A710_3701772 */
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#if ERRATA_A715_3699560
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case EXTRACT_PARTNUM(CORTEX_A715_MIDR):
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if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A715_3699560 */
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#if ERRATA_A720_3699561
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case EXTRACT_PARTNUM(CORTEX_A720_MIDR):
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if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;;
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break;
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#endif /* ERRATA_A720_3699561 */
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#if ERRATA_A720_AE_3699562
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case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
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if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A720_AE_3699562 */
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#if ERRATA_A725_3699564
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case EXTRACT_PARTNUM(CORTEX_A725_MIDR):
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if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A725_3699564 */
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#if ERRATA_X2_3701772
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case EXTRACT_PARTNUM(CORTEX_X2_MIDR):
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if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X2_3701772 */
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#if ERRATA_X3_3701769
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case EXTRACT_PARTNUM(CORTEX_X3_MIDR):
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if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X3_3701769 */
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#if ERRATA_X4_3701758
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case EXTRACT_PARTNUM(CORTEX_X4_MIDR):
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if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X4_3701758 */
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#if ERRATA_X925_3701747
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case EXTRACT_PARTNUM(CORTEX_X925_MIDR):
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if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X925_3701747 */
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#if ERRATA_N2_3701773
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case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR):
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if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_N2_3701773 */
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#if ERRATA_N3_3699563
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case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR):
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if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_N3_3699563 */
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#if ERRATA_V3_3701767
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case EXTRACT_PARTNUM(NEOVERSE_V3_MIDR):
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if (check_erratum_neoverse_v3_3701767(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_V3_3701767 */
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default:
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break;
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}
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return false;
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}
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