mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
6595f4cb39
This patch fixes a bug which was introduced in commit
3065513 related to improper saving of EL1 context in the
context management library code when using 128-bit
system registers.
Bug explanation:
The function el1_sysregs_context_save still used the normal
macros that read all the system registers related to the EL1
context, which then involved casting them to uint64_t and
eventually writing them to a memory structure. This means that
the context management library was saving EL1-related SYSREG128
registers with the upper 64 bits zeroed out.
Alternative macros had previously been introduced for the EL2
context in the aforementioned commit, but not for EL1.
Some refactoring has also been done as part of this patch:
- Re-added "common" back to write_el2_ctx_common_sysreg128
- Added dummy SYSREG128 macros for cases when some features
are disabled
- Removed some newlines
Change-Id: I15aa2190794ac099a493e5f430220b1c81e1b558
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
328 lines
8 KiB
C
328 lines
8 KiB
C
/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_EL1_H
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#define CONTEXT_EL1_H
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#include <lib/extensions/sysreg128.h>
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#ifndef __ASSEMBLER__
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/*******************************************************************************
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* EL1 Registers:
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* AArch64 EL1 system register context structure for preserving the
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* architectural state during world switches.
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******************************************************************************/
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typedef struct el1_common_regs {
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uint64_t spsr_el1;
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uint64_t elr_el1;
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#if (!ERRATA_SPECULATIVE_AT)
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uint64_t sctlr_el1;
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uint64_t tcr_el1;
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#endif /* ERRATA_SPECULATIVE_AT=0 */
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uint64_t cpacr_el1;
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uint64_t csselr_el1;
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uint64_t sp_el1;
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uint64_t esr_el1;
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uint64_t mair_el1;
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uint64_t amair_el1;
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uint64_t actlr_el1;
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uint64_t tpidr_el1;
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uint64_t tpidr_el0;
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uint64_t tpidrro_el0;
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uint64_t far_el1;
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uint64_t afsr0_el1;
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uint64_t afsr1_el1;
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uint64_t contextidr_el1;
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uint64_t vbar_el1;
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uint64_t mdccint_el1;
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uint64_t mdscr_el1;
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sysreg_t par_el1;
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sysreg_t ttbr0_el1;
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sysreg_t ttbr1_el1;
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} el1_common_regs_t;
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typedef struct el1_aarch32_regs {
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uint64_t spsr_abt;
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uint64_t spsr_und;
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uint64_t spsr_irq;
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uint64_t spsr_fiq;
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uint64_t dacr32_el2;
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uint64_t ifsr32_el2;
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} el1_aarch32_regs_t;
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typedef struct el1_arch_timer_regs {
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uint64_t cntp_ctl_el0;
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uint64_t cntp_cval_el0;
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uint64_t cntv_ctl_el0;
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uint64_t cntv_cval_el0;
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uint64_t cntkctl_el1;
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} el1_arch_timer_regs_t;
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typedef struct el1_mte2_regs {
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uint64_t tfsre0_el1;
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uint64_t tfsr_el1;
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uint64_t rgsr_el1;
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uint64_t gcr_el1;
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} el1_mte2_regs_t;
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typedef struct el1_ras_regs {
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uint64_t disr_el1;
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} el1_ras_regs_t;
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typedef struct el1_s1pie_regs {
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uint64_t pire0_el1;
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uint64_t pir_el1;
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} el1_s1pie_regs_t;
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typedef struct el1_s1poe_regs {
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uint64_t por_el1;
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} el1_s1poe_regs_t;
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typedef struct el1_s2poe_regs {
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uint64_t s2por_el1;
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} el1_s2poe_regs_t;
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typedef struct el1_tcr2_regs {
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uint64_t tcr2_el1;
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} el1_tcr2_regs_t;
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typedef struct el1_trf_regs {
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uint64_t trfcr_el1;
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} el1_trf_regs_t;
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typedef struct el1_csv2_2_regs {
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uint64_t scxtnum_el0;
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uint64_t scxtnum_el1;
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} el1_csv2_2_regs_t;
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typedef struct el1_gcs_regs {
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uint64_t gcscr_el1;
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uint64_t gcscre0_el1;
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uint64_t gcspr_el1;
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uint64_t gcspr_el0;
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} el1_gcs_regs_t;
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typedef struct el1_the_regs {
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sysreg_t rcwmask_el1;
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sysreg_t rcwsmask_el1;
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} el1_the_regs_t;
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typedef struct el1_sctlr2_regs {
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uint64_t sctlr2_el1;
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} el1_sctlr2_regs_t;
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typedef struct el1_ls64_regs {
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uint64_t accdata_el1;
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} el1_ls64_regs_t;
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typedef struct el1_sysregs {
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el1_common_regs_t common;
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#if CTX_INCLUDE_AARCH32_REGS
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el1_aarch32_regs_t el1_aarch32;
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#endif
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#if NS_TIMER_SWITCH
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el1_arch_timer_regs_t arch_timer;
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#endif
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#if ENABLE_FEAT_MTE2
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el1_mte2_regs_t mte2;
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#endif
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#if ENABLE_FEAT_RAS
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el1_ras_regs_t ras;
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#endif
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#if ENABLE_FEAT_S1PIE
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el1_s1pie_regs_t s1pie;
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#endif
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#if ENABLE_FEAT_S1POE
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el1_s1poe_regs_t s1poe;
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#endif
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#if ENABLE_FEAT_S2POE
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el1_s2poe_regs_t s2poe;
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#endif
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#if ENABLE_FEAT_TCR2
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el1_tcr2_regs_t tcr2;
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#endif
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#if ENABLE_TRF_FOR_NS
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el1_trf_regs_t trf;
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#endif
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#if ENABLE_FEAT_CSV2_2
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el1_csv2_2_regs_t csv2_2;
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#endif
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#if ENABLE_FEAT_GCS
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el1_gcs_regs_t gcs;
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#endif
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#if ENABLE_FEAT_THE
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el1_the_regs_t the;
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#endif
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#if ENABLE_FEAT_SCTLR2
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el1_sctlr2_regs_t sctlr2;
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#endif
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#if ENABLE_FEAT_LS64_ACCDATA
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el1_ls64_regs_t ls64;
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#endif
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} el1_sysregs_t;
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/*
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* Macros to access members related to individual features of the el1_sysregs_t
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* structures.
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*/
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#define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg)
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#define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \
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= (uint64_t) (val))
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#define write_el1_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \
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= (sysreg_t) (val))
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#if NS_TIMER_SWITCH
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#define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg)
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#define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_arch_timer(ctx, reg) ULL(0)
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#define write_el1_ctx_arch_timer(ctx, reg, val)
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#endif /* NS_TIMER_SWITCH */
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#if CTX_INCLUDE_AARCH32_REGS
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#define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg)
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#define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_aarch32(ctx, reg) ULL(0)
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#define write_el1_ctx_aarch32(ctx, reg, val)
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#endif /* CTX_INCLUDE_AARCH32_REGS */
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#if ENABLE_FEAT_MTE2
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#define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg)
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#define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_mte2(ctx, reg) ULL(0)
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#define write_el1_ctx_mte2(ctx, reg, val)
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#endif /* ENABLE_FEAT_MTE2 */
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#if ENABLE_FEAT_RAS
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#define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg)
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#define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_ras(ctx, reg) ULL(0)
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#define write_el1_ctx_ras(ctx, reg, val)
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#endif /* ENABLE_FEAT_RAS */
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#if ENABLE_FEAT_S1PIE
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#define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg)
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#define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s1pie(ctx, reg) ULL(0)
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#define write_el1_ctx_s1pie(ctx, reg, val)
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#endif /* ENABLE_FEAT_S1PIE */
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#if ENABLE_FEAT_S1POE
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#define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg)
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#define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s1poe(ctx, reg) ULL(0)
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#define write_el1_ctx_s1poe(ctx, reg, val)
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#endif /* ENABLE_FEAT_S1POE */
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#if ENABLE_FEAT_S2POE
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#define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg)
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#define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s2poe(ctx, reg) ULL(0)
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#define write_el1_ctx_s2poe(ctx, reg, val)
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#endif /* ENABLE_FEAT_S2POE */
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#if ENABLE_FEAT_TCR2
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#define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg)
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#define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_tcr2(ctx, reg) ULL(0)
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#define write_el1_ctx_tcr2(ctx, reg, val)
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#endif /* ENABLE_FEAT_TCR2 */
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#if ENABLE_TRF_FOR_NS
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#define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg)
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#define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_trf(ctx, reg) ULL(0)
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#define write_el1_ctx_trf(ctx, reg, val)
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#endif /* ENABLE_TRF_FOR_NS */
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#if ENABLE_FEAT_CSV2_2
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#define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg)
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#define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_csv2_2(ctx, reg) ULL(0)
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#define write_el1_ctx_csv2_2(ctx, reg, val)
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#endif /* ENABLE_FEAT_CSV2_2 */
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#if ENABLE_FEAT_GCS
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#define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg)
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#define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_gcs(ctx, reg) ULL(0)
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#define write_el1_ctx_gcs(ctx, reg, val)
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#endif /* ENABLE_FEAT_GCS */
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#if ENABLE_FEAT_THE
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#define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg)
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#define write_el1_ctx_the_sysreg128(ctx, reg, val) ((((ctx)->the).reg) \
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= (sysreg_t) (val))
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#else
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#define read_el1_ctx_the(ctx, reg) ULL(0)
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#define write_el1_ctx_the_sysreg128(ctx, reg, val)
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#endif /* ENABLE_FEAT_THE */
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#if ENABLE_FEAT_SCTLR2
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#define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
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#define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_sctlr2(ctx, reg) ULL(0)
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#define write_el1_ctx_sctlr2(ctx, reg, val)
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#endif /* ENABLE_FEAT_SCTLR2 */
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#if ENABLE_FEAT_LS64_ACCDATA
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#define read_el1_ctx_ls64(ctx, reg) (((ctx)->ls64).reg)
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#define write_el1_ctx_ls64(ctx, reg, val) ((((ctx)->ls64).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_ls64(ctx, reg) ULL(0)
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#define write_el1_ctx_ls64(ctx, reg, val)
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#endif /* ENABLE_FEAT_LS64_ACCDATA */
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/******************************************************************************/
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#endif /* __ASSEMBLER__ */
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#endif /* CONTEXT_EL1_H */
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