mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-30 07:39:24 +00:00
fcf2ab71ac
Cortex-A715 erratum 2804830 applies to r0p0, r1p0, r1p1 and r1p2, and is fixed in r1p3. Under some conditions, writes of a 64B-aligned, 64B granule of memory might cause data corruption without this workaround. See SDEN for details. Since this workaround disables write streaming, it is expected to have a significant performance impact for code that is heavily reliant on write streaming, such as memcpy or memset. SDEN: https://developer.arm.com/documentation/SDEN-2148827/latest/ Change-Id: Ia12f6c7de7c92f6ea4aec3057b228b828d48724c Signed-off-by: John Powell <john.powell@arm.com>
39 lines
1.4 KiB
C
39 lines
1.4 KiB
C
/*
|
|
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef CORTEX_A715_H
|
|
#define CORTEX_A715_H
|
|
|
|
#define CORTEX_A715_MIDR U(0x410FD4D0)
|
|
|
|
/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
|
|
#define CORTEX_A715_BHB_LOOP_COUNT U(38)
|
|
|
|
/*******************************************************************************
|
|
* CPU Register Mappings
|
|
******************************************************************************/
|
|
#define CORTEX_A715_CPUCFR_EL1 S3_0_C15_C0_0
|
|
#define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0
|
|
#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
|
|
#define CORTEX_A715_CPUACTLR3_EL1 S3_0_C15_C1_2
|
|
#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
|
|
#define CORTEX_A715_CPUECTLR2_EL1 S3_0_C15_C1_5
|
|
#define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0
|
|
#define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1
|
|
#define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2
|
|
#define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3
|
|
|
|
/*******************************************************************************
|
|
* CPU Power Control register specific definitions
|
|
******************************************************************************/
|
|
#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
|
|
|
#ifndef __ASSEMBLER__
|
|
long check_erratum_cortex_a715_3699560(long cpu_rev);
|
|
#endif /* __ASSEMBLER__ */
|
|
|
|
#endif /* CORTEX_A715_H */
|