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https://github.com/ARM-software/arm-trusted-firmware.git
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817f42f07e
The STPMIC2 embeds 15 regulators with various properties, and is designed to supply the STM32MP2 SOC. This driver handles a minimal set of feature to handle the boot of a board. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e
307 lines
7.7 KiB
C
307 lines
7.7 KiB
C
/*
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* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STPMIC2_H
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#define STPMIC2_H
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#include <drivers/st/stm32_i2c.h>
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#include <lib/utils_def.h>
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enum {
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STPMIC2_BUCK1 = 0,
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STPMIC2_BUCK2,
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STPMIC2_BUCK3,
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STPMIC2_BUCK4,
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STPMIC2_BUCK5,
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STPMIC2_BUCK6,
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STPMIC2_BUCK7,
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STPMIC2_REFDDR,
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STPMIC2_LDO1,
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STPMIC2_LDO2,
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STPMIC2_LDO3,
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STPMIC2_LDO4,
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STPMIC2_LDO5,
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STPMIC2_LDO6,
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STPMIC2_LDO7,
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STPMIC2_LDO8,
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STPMIC2_NB_REG
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};
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/* Status Registers */
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#define PRODUCT_ID 0x00
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#define VERSION_SR 0x01
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#define TURN_ON_SR 0x02
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#define TURN_OFF_SR 0x03
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#define RESTART_SR 0x04
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#define OCP_SR1 0x05
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#define OCP_SR2 0x06
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#define EN_SR1 0x07
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#define EN_SR2 0x08
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#define FS_CNT_SR1 0x09
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#define FS_CNT_SR2 0x0A
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#define FS_CNT_SR3 0x0B
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#define MODE_SR 0x0C
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/* Control Registers */
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#define MAIN_CR 0x10
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#define VINLOW_CR 0x11
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#define PKEY_LKP_CR 0x12
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#define WDG_CR 0x13
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#define WDG_TMR_CR 0x14
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#define WDG_TMR_SR 0x15
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#define FS_OCP_CR1 0x16
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#define FS_OCP_CR2 0x17
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#define PADS_PULL_CR 0x18
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#define BUCKS_PD_CR1 0x19
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#define BUCKS_PD_CR2 0x1A
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#define LDOS_PD_CR1 0x1B
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#define LDOS_PD_CR2 0x1C
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#define BUCKS_MRST_CR 0x1D
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#define LDOS_MRST_CR 0x1E
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/* Buck CR */
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#define BUCK1_MAIN_CR1 0x20
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#define BUCK1_MAIN_CR2 0x21
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#define BUCK1_ALT_CR1 0x22
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#define BUCK1_ALT_CR2 0x23
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#define BUCK1_PWRCTRL_CR 0x24
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#define BUCK2_MAIN_CR1 0x25
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#define BUCK2_MAIN_CR2 0x26
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#define BUCK2_ALT_CR1 0x27
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#define BUCK2_ALT_CR2 0x28
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#define BUCK2_PWRCTRL_CR 0x29
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#define BUCK3_MAIN_CR1 0x2A
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#define BUCK3_MAIN_CR2 0x2B
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#define BUCK3_ALT_CR1 0x2C
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#define BUCK3_ALT_CR2 0x2D
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#define BUCK3_PWRCTRL_CR 0x2E
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#define BUCK4_MAIN_CR1 0x2F
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#define BUCK4_MAIN_CR2 0x30
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#define BUCK4_ALT_CR1 0x31
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#define BUCK4_ALT_CR2 0x32
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#define BUCK4_PWRCTRL_CR 0x33
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#define BUCK5_MAIN_CR1 0x34
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#define BUCK5_MAIN_CR2 0x35
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#define BUCK5_ALT_CR1 0x36
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#define BUCK5_ALT_CR2 0x37
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#define BUCK5_PWRCTRL_CR 0x38
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#define BUCK6_MAIN_CR1 0x39
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#define BUCK6_MAIN_CR2 0x3A
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#define BUCK6_ALT_CR1 0x3B
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#define BUCK6_ALT_CR2 0x3C
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#define BUCK6_PWRCTRL_CR 0x3D
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#define BUCK7_MAIN_CR1 0x3E
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#define BUCK7_MAIN_CR2 0x3F
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#define BUCK7_ALT_CR1 0x40
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#define BUCK7_ALT_CR2 0x41
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#define BUCK7_PWRCTRL_CR 0x42
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/* LDO CR */
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#define LDO1_MAIN_CR 0x4C
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#define LDO1_ALT_CR 0x4D
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#define LDO1_PWRCTRL_CR 0x4E
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#define LDO2_MAIN_CR 0x4F
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#define LDO2_ALT_CR 0x50
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#define LDO2_PWRCTRL_CR 0x51
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#define LDO3_MAIN_CR 0x52
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#define LDO3_ALT_CR 0x53
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#define LDO3_PWRCTRL_CR 0x54
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#define LDO4_MAIN_CR 0x55
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#define LDO4_ALT_CR 0x56
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#define LDO4_PWRCTRL_CR 0x57
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#define LDO5_MAIN_CR 0x58
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#define LDO5_ALT_CR 0x59
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#define LDO5_PWRCTRL_CR 0x5A
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#define LDO6_MAIN_CR 0x5B
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#define LDO6_ALT_CR 0x5C
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#define LDO6_PWRCTRL_CR 0x5D
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#define LDO7_MAIN_CR 0x5E
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#define LDO7_ALT_CR 0x5F
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#define LDO7_PWRCTRL_CR 0x60
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#define LDO8_MAIN_CR 0x61
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#define LDO8_ALT_CR 0x62
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#define LDO8_PWRCTRL_CR 0x63
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#define REFDDR_MAIN_CR 0x64
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#define REFDDR_ALT_CR 0x65
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#define REFDDR_PWRCTRL_CR 0x66
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/* INTERRUPT CR */
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#define INT_PENDING_R1 0x70
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#define INT_PENDING_R2 0x71
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#define INT_PENDING_R3 0x72
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#define INT_PENDING_R4 0x73
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#define INT_CLEAR_R1 0x74
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#define INT_CLEAR_R2 0x75
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#define INT_CLEAR_R3 0x76
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#define INT_CLEAR_R4 0x77
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#define INT_MASK_R1 0x78
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#define INT_MASK_R2 0x79
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#define INT_MASK_R3 0x7A
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#define INT_MASK_R4 0x7B
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#define INT_SRC_R1 0x7C
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#define INT_SRC_R2 0x7D
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#define INT_SRC_R3 0x7E
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#define INT_SRC_R4 0x7F
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#define INT_DBG_LATCH_R1 0x80
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#define INT_DBG_LATCH_R2 0x81
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#define INT_DBG_LATCH_R3 0x82
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#define INT_DBG_LATCH_R4 0x83
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/* BUCKS_MRST_CR bits definition */
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#define BUCK1_MRST BIT(0)
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#define BUCK2_MRST BIT(1)
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#define BUCK3_MRST BIT(2)
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#define BUCK4_MRST BIT(3)
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#define BUCK5_MRST BIT(4)
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#define BUCK6_MRST BIT(5)
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#define BUCK7_MRST BIT(6)
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#define REFDDR_MRST BIT(7)
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/* LDOS_MRST_CR bits definition */
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#define LDO1_MRST BIT(0)
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#define LDO2_MRST BIT(1)
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#define LDO3_MRST BIT(2)
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#define LDO4_MRST BIT(3)
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#define LDO5_MRST BIT(4)
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#define LDO6_MRST BIT(5)
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#define LDO7_MRST BIT(6)
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#define LDO8_MRST BIT(7)
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/* LDOx_MAIN_CR */
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#define LDO_VOLT_SHIFT 1
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#define LDO_BYPASS BIT(6)
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#define LDO1_INPUT_SRC BIT(7)
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#define LDO3_SNK_SRC BIT(7)
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#define LDO4_INPUT_SRC_SHIFT 6
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#define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6)
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/* PWRCTRL register bit definition */
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#define PWRCTRL_EN BIT(0)
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#define PWRCTRL_RS BIT(1)
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#define PWRCTRL_SEL_SHIFT 2
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#define PWRCTRL_SEL_MASK GENMASK_32(3, 2)
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/* BUCKx_MAIN_CR2 */
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#define PREG_MODE_SHIFT 1
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#define PREG_MODE_MASK GENMASK_32(2, 1)
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/* BUCKS_PD_CR1 */
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#define BUCK1_PD_MASK GENMASK_32(1, 0)
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#define BUCK2_PD_MASK GENMASK_32(3, 2)
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#define BUCK3_PD_MASK GENMASK_32(5, 4)
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#define BUCK4_PD_MASK GENMASK_32(7, 6)
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#define BUCK1_PD_FAST BIT(1)
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#define BUCK2_PD_FAST BIT(3)
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#define BUCK3_PD_FAST BIT(5)
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#define BUCK4_PD_FAST BIT(7)
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/* BUCKS_PD_CR2 */
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#define BUCK5_PD_MASK GENMASK_32(1, 0)
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#define BUCK6_PD_MASK GENMASK_32(3, 2)
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#define BUCK7_PD_MASK GENMASK_32(5, 4)
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#define BUCK5_PD_FAST BIT(1)
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#define BUCK6_PD_FAST BIT(3)
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#define BUCK7_PD_FAST BIT(5)
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/* LDOS_PD_CR1 */
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#define LDO1_PD BIT(0)
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#define LDO2_PD BIT(1)
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#define LDO3_PD BIT(2)
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#define LDO4_PD BIT(3)
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#define LDO5_PD BIT(4)
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#define LDO6_PD BIT(5)
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#define LDO7_PD BIT(6)
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#define LDO8_PD BIT(7)
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/* LDOS_PD_CR2 */
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#define REFDDR_PD BIT(0)
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/* FS_OCP_CR1 */
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#define FS_OCP_BUCK1 BIT(0)
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#define FS_OCP_BUCK2 BIT(1)
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#define FS_OCP_BUCK3 BIT(2)
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#define FS_OCP_BUCK4 BIT(3)
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#define FS_OCP_BUCK5 BIT(4)
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#define FS_OCP_BUCK6 BIT(5)
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#define FS_OCP_BUCK7 BIT(6)
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#define FS_OCP_REFDDR BIT(7)
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/* FS_OCP_CR2 */
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#define FS_OCP_LDO1 BIT(0)
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#define FS_OCP_LDO2 BIT(1)
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#define FS_OCP_LDO3 BIT(2)
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#define FS_OCP_LDO4 BIT(3)
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#define FS_OCP_LDO5 BIT(4)
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#define FS_OCP_LDO6 BIT(5)
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#define FS_OCP_LDO7 BIT(6)
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#define FS_OCP_LDO8 BIT(7)
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/* IRQ definitions */
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#define IT_PONKEY_F 0
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#define IT_PONKEY_R 1
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#define IT_BUCK1_OCP 16
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#define IT_BUCK2_OCP 17
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#define IT_BUCK3_OCP 18
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#define IT_BUCK4_OCP 19
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#define IT_BUCK5_OCP 20
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#define IT_BUCK6_OCP 21
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#define IT_BUCK7_OCP 22
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#define IT_REFDDR_OCP 23
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#define IT_LDO1_OCP 24
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#define IT_LDO2_OCP 25
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#define IT_LDO3_OCP 26
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#define IT_LDO4_OCP 27
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#define IT_LDO5_OCP 28
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#define IT_LDO6_OCP 29
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#define IT_LDO7_OCP 30
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#define IT_LDO8_OCP 31
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enum stpmic2_prop_id {
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STPMIC2_MASK_RESET = 0,
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STPMIC2_PULL_DOWN,
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STPMIC2_BYPASS, /* arg: 1=set 0=reset */
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STPMIC2_SINK_SOURCE,
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STPMIC2_OCP,
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};
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struct pmic_handle_s {
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struct i2c_handle_s *i2c_handle;
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uint32_t i2c_addr;
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unsigned int pmic_status;
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};
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int stpmic2_register_read(struct pmic_handle_s *pmic,
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uint8_t register_id, uint8_t *value);
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int stpmic2_register_write(struct pmic_handle_s *pmic,
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uint8_t register_id, uint8_t value);
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int stpmic2_register_update(struct pmic_handle_s *pmic,
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uint8_t register_id, uint8_t value, uint8_t mask);
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int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
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uint8_t id, bool enable);
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int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
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uint8_t id, bool *enabled);
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int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
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uint8_t id, const uint16_t **levels,
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size_t *levels_count);
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int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
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uint8_t id, uint16_t *val);
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int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
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uint8_t id, uint16_t millivolts);
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#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
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void stpmic2_dump_regulators(struct pmic_handle_s *pmic);
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#endif
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int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val);
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int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val);
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int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
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enum stpmic2_prop_id prop);
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int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
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enum stpmic2_prop_id prop, uint32_t arg);
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#endif /*STPMIC2_H*/
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