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https://github.com/ARM-software/arm-trusted-firmware.git
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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef STM32MP_DDR_H
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#define STM32MP_DDR_H
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#include <platform_def.h>
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enum stm32mp_ddr_base_type {
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DDR_BASE,
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DDRPHY_BASE,
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NONE_BASE
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};
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enum stm32mp_ddr_reg_type {
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REG_REG,
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REG_TIMING,
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REG_PERF,
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REG_MAP,
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REGPHY_REG,
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REGPHY_TIMING,
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REG_TYPE_NB
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};
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struct stm32mp_ddr_reg_desc {
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uint16_t offset; /* Offset for base address */
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uint8_t par_offset; /* Offset for parameter array */
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#if !STM32MP13 && !STM32MP15
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bool qd; /* quasi-dynamic register if true */
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#endif
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};
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struct stm32mp_ddr_reg_info {
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const char *name;
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const struct stm32mp_ddr_reg_desc *desc;
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uint8_t size;
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enum stm32mp_ddr_base_type base;
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};
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struct stm32mp_ddr_size {
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uint64_t base;
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uint64_t size;
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};
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struct stm32mp_ddr_priv {
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struct stm32mp_ddr_size info;
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struct stm32mp_ddrctl *ctl;
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struct stm32mp_ddrphy *phy;
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uintptr_t pwr;
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uintptr_t rcc;
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};
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struct stm32mp_ddr_info {
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const char *name;
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uint32_t speed; /* in kHz */
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size_t size; /* Memory size in byte = col * row * width */
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};
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#define DDR_DELAY_1US 1U
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#define DDR_DELAY_2US 2U
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#define DDR_DELAY_10US 10U
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#define DDR_DELAY_50US 50U
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#define DDR_TIMEOUT_500US 500U
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#define DDR_TIMEOUT_US_1S 1000000U
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void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
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const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
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void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
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int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl);
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int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl);
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int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
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#endif /* STM32MP_DDR_H */
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