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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef STM32MP2_DDR_REGS_H
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#define STM32MP2_DDR_REGS_H
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#include <drivers/st/stm32mp_ddrctrl_regs.h>
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#include <lib/utils_def.h>
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/* DDR Physical Interface Control (DDRPHYC) registers*/
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struct stm32mp_ddrphy {
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uint32_t dummy;
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} __packed;
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/* DDRPHY registers offsets */
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#define DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6 U(0x240004)
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#define DDRPHY_INITENG0_P0_PHYINLPX U(0x2400A0)
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#define DDRPHY_DRTUB0_UCCLKHCLKENABLES U(0x300200)
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#define DDRPHY_APBONLY0_MICROCONTMUXSEL U(0x340000)
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/* DDRPHY registers fields */
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#define DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3 BIT(0)
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#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN BIT(0)
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#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN BIT(1)
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#define DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL BIT(0)
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/* DDRDBG registers offsets */
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#define DDRDBG_LP_DISABLE U(0x0)
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#define DDRDBG_BYPASS_PCLKEN U(0x4)
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/* DDRDBG registers fields */
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#define DDRDBG_LP_DISABLE_LPI_XPI_DISABLE BIT(0)
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#define DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE BIT(8)
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#endif /* STM32MP2_DDR_REGS_H */
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