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https://github.com/ARM-software/arm-trusted-firmware.git
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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
147 lines
2.9 KiB
C
147 lines
2.9 KiB
C
/*
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* Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef STM32MP2_DDR_H
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#define STM32MP2_DDR_H
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#include <stdbool.h>
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#include <ddrphy_phyinit_struct.h>
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#include <drivers/st/stm32mp_ddr.h>
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struct stm32mp2_ddrctrl_reg {
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uint32_t mstr;
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uint32_t mrctrl0;
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uint32_t mrctrl1;
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uint32_t mrctrl2;
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uint32_t derateen;
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uint32_t derateint;
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uint32_t deratectl;
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uint32_t pwrctl;
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uint32_t pwrtmg;
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uint32_t hwlpctl;
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uint32_t rfshctl0;
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uint32_t rfshctl1;
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uint32_t rfshctl3;
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uint32_t crcparctl0;
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uint32_t crcparctl1;
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uint32_t init0;
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uint32_t init1;
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uint32_t init2;
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uint32_t init3;
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uint32_t init4;
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uint32_t init5;
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uint32_t init6;
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uint32_t init7;
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uint32_t dimmctl;
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uint32_t rankctl;
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uint32_t rankctl1;
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uint32_t zqctl0;
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uint32_t zqctl1;
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uint32_t zqctl2;
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uint32_t dfitmg0;
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uint32_t dfitmg1;
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uint32_t dfilpcfg0;
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uint32_t dfilpcfg1;
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uint32_t dfiupd0;
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uint32_t dfiupd1;
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uint32_t dfiupd2;
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uint32_t dfimisc;
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uint32_t dfitmg2;
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uint32_t dfitmg3;
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uint32_t dbictl;
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uint32_t dfiphymstr;
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uint32_t dbg0;
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uint32_t dbg1;
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uint32_t dbgcmd;
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uint32_t swctl;
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uint32_t swctlstatic;
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uint32_t poisoncfg;
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uint32_t pccfg;
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};
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struct stm32mp2_ddrctrl_timing {
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uint32_t rfshtmg;
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uint32_t rfshtmg1;
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uint32_t dramtmg0;
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uint32_t dramtmg1;
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uint32_t dramtmg2;
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uint32_t dramtmg3;
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uint32_t dramtmg4;
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uint32_t dramtmg5;
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uint32_t dramtmg6;
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uint32_t dramtmg7;
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uint32_t dramtmg8;
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uint32_t dramtmg9;
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uint32_t dramtmg10;
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uint32_t dramtmg11;
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uint32_t dramtmg12;
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uint32_t dramtmg13;
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uint32_t dramtmg14;
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uint32_t dramtmg15;
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uint32_t odtcfg;
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uint32_t odtmap;
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};
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struct stm32mp2_ddrctrl_map {
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uint32_t addrmap0;
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uint32_t addrmap1;
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uint32_t addrmap2;
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uint32_t addrmap3;
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uint32_t addrmap4;
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uint32_t addrmap5;
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uint32_t addrmap6;
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uint32_t addrmap7;
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uint32_t addrmap8;
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uint32_t addrmap9;
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uint32_t addrmap10;
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uint32_t addrmap11;
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};
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struct stm32mp2_ddrctrl_perf {
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uint32_t sched;
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uint32_t sched1;
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uint32_t perfhpr1;
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uint32_t perflpr1;
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uint32_t perfwr1;
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uint32_t sched3;
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uint32_t sched4;
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uint32_t pcfgr_0;
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uint32_t pcfgw_0;
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uint32_t pctrl_0;
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uint32_t pcfgqos0_0;
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uint32_t pcfgqos1_0;
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uint32_t pcfgwqos0_0;
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uint32_t pcfgwqos1_0;
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#if STM32MP_DDR_DUAL_AXI_PORT
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uint32_t pcfgr_1;
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uint32_t pcfgw_1;
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uint32_t pctrl_1;
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uint32_t pcfgqos0_1;
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uint32_t pcfgqos1_1;
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uint32_t pcfgwqos0_1;
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uint32_t pcfgwqos1_1;
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#endif /* STM32MP_DDR_DUAL_AXI_PORT */
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};
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struct stm32mp_ddr_config {
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struct stm32mp_ddr_info info;
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struct stm32mp2_ddrctrl_reg c_reg;
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struct stm32mp2_ddrctrl_timing c_timing;
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struct stm32mp2_ddrctrl_map c_map;
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struct stm32mp2_ddrctrl_perf c_perf;
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bool self_refresh;
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uint32_t zdata;
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struct user_input_basic uib;
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struct user_input_advanced uia;
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struct user_input_mode_register uim;
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struct user_input_swizzle uis;
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};
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void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config);
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#endif /* STM32MP2_DDR_H */
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