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da7a33cf2f
The framework currently supports QE feature only for Macronix devices. Kioxia devices also support this feature, but this feature can not be set based on the manufacturer ID as Kioxia first SPI NAND generation does not support the QE feature when the second generation does. Use a flag to manage QE feature. This flag will be added at board level to manage the device. Change-Id: I7a3683a2df8739967b17b4abbec32c51bf206b93 Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/*
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* Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_SPI_NAND_H
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#define DRIVERS_SPI_NAND_H
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#include <drivers/nand.h>
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#include <drivers/spi_mem.h>
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#define SPI_NAND_OP_GET_FEATURE 0x0FU
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#define SPI_NAND_OP_SET_FEATURE 0x1FU
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#define SPI_NAND_OP_READ_ID 0x9FU
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#define SPI_NAND_OP_LOAD_PAGE 0x13U
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#define SPI_NAND_OP_RESET 0xFFU
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#define SPI_NAND_OP_READ_FROM_CACHE 0x03U
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#define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU
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#define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU
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/* Configuration register */
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#define SPI_NAND_REG_CFG 0xB0U
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#define SPI_NAND_CFG_ECC_EN BIT(4)
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#define SPI_NAND_CFG_QE BIT(0)
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/* Status register */
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#define SPI_NAND_REG_STATUS 0xC0U
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#define SPI_NAND_STATUS_BUSY BIT(0)
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#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
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/* Flags for specific configuration */
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#define SPI_NAND_HAS_QE_BIT BIT(0)
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struct spinand_device {
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struct nand_device *nand_dev;
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struct spi_mem_op spi_read_cache_op;
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uint32_t flags;
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uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
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};
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int spi_nand_init(unsigned long long *size, unsigned int *erase_size);
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/*
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* Platform can implement this to override default SPI-NAND instance
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* configuration.
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*
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* @device: target SPI-NAND instance.
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* Return 0 on success, negative value otherwise.
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*/
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int plat_get_spi_nand_data(struct spinand_device *device);
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#endif /* DRIVERS_SPI_NAND_H */
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