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https://github.com/ARM-software/arm-trusted-firmware.git
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050a99a62f
NXP drivers header files are moved: - from: drivers/nxp/<xx>/*.h - to : include/drivers/nxp/<xx>/*.h To accommodate these changes each drivers makefiles drivers/nxp/<xx>/xx.mk, are updated. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PMU_H
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#define PMU_H
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/* PMU Registers' OFFSET */
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#define PMU_PCPW20SR_OFFSET 0x830
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#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
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#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
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#define PMU_CLL2FLUSHSR_OFFSET 0x1118
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#define PMU_POWMGTCSR_VAL (1 << 20)
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/* PMU Registers */
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#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0
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#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0
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#define PMU_IDLE_CLUSTER_MASK 0x2
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#define PMU_FLUSH_CLUSTER_MASK 0x2
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#define PMU_IDLE_CORE_MASK 0xfe
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/* pmu register offsets and bitmaps */
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#define PMU_POWMGTDCR0_OFFSET 0xC20
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#define PMU_POWMGTCSR_OFFSET 0x4000
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#define PMU_CLAINACTSETR_OFFSET 0x1100
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#define PMU_CLAINACTCLRR_OFFSET 0x1104
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#define PMU_CLSINACTSETR_OFFSET 0x1108
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#define PMU_CLSINACTCLRR_OFFSET 0x110C
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#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
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#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114
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#define PMU_IPPDEXPCR0_OFFSET 0x4040
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#define PMU_IPPDEXPCR1_OFFSET 0x4044
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#define PMU_IPPDEXPCR2_OFFSET 0x4048
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#define PMU_IPPDEXPCR3_OFFSET 0x404C
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#define PMU_IPPDEXPCR4_OFFSET 0x4050
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#define PMU_IPPDEXPCR5_OFFSET 0x4054
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#define PMU_IPPDEXPCR6_OFFSET 0x4058
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#define PMU_IPSTPCR0_OFFSET 0x4120
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#define PMU_IPSTPCR1_OFFSET 0x4124
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#define PMU_IPSTPCR2_OFFSET 0x4128
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#define PMU_IPSTPCR3_OFFSET 0x412C
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#define PMU_IPSTPCR4_OFFSET 0x4130
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#define PMU_IPSTPCR5_OFFSET 0x4134
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#define PMU_IPSTPCR6_OFFSET 0x4138
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#define PMU_IPSTPACKSR0_OFFSET 0x4140
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#define PMU_IPSTPACKSR1_OFFSET 0x4144
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#define PMU_IPSTPACKSR2_OFFSET 0x4148
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#define PMU_IPSTPACKSR3_OFFSET 0x414C
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#define PMU_IPSTPACKSR4_OFFSET 0x4150
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#define PMU_IPSTPACKSR5_OFFSET 0x4154
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#define PMU_IPSTPACKSR6_OFFSET 0x4158
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#define CLAINACT_DISABLE_ACP 0xFF
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#define CLSINACT_DISABLE_SKY 0xFF
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#define POWMGTDCR_STP_OV_EN 0x1
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#define POWMGTCSR_LPM20_REQ 0x00100000
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/* Used by PMU */
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#define DEVDISR1_MASK 0x024F3504
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#define DEVDISR2_MASK 0x0003FFFF
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#define DEVDISR3_MASK 0x0000303F
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#define DEVDISR4_MASK 0x0000FFFF
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#define DEVDISR5_MASK 0x00F07603
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#define DEVDISR6_MASK 0x00000001
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#ifndef __ASSEMBLER__
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void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr);
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void enable_core_tb(uintptr_t nxp_pmu_addr);
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#endif /* __ASSEMBLER__ */
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#endif
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