mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
479 lines
14 KiB
C
479 lines
14 KiB
C
/*
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* Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <common/debug.h>
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#include <ddrphy_phyinit.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32mp2_ddr_helpers.h>
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#include <drivers/st/stm32mp2_ddr_regs.h>
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#include <drivers/st/stm32mp_ddr.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define DDRDBG_FRAC_PLL_LOCK U(0x10)
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#define DDRCTL_REG(x, y, z) \
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{ \
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.offset = offsetof(struct stm32mp_ddrctl, x), \
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.par_offset = offsetof(struct y, x), \
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.qd = z \
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}
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/*
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* PARAMETERS: value get from device tree :
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* size / order need to be aligned with binding
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* modification NOT ALLOWED !!!
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*/
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#define DDRCTL_REG_REG_SIZE 48 /* st,ctl-reg */
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#define DDRCTL_REG_TIMING_SIZE 20 /* st,ctl-timing */
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#define DDRCTL_REG_MAP_SIZE 12 /* st,ctl-map */
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#if STM32MP_DDR_DUAL_AXI_PORT
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#define DDRCTL_REG_PERF_SIZE 21 /* st,ctl-perf */
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#else /* !STM32MP_DDR_DUAL_AXI_PORT */
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#define DDRCTL_REG_PERF_SIZE 14 /* st,ctl-perf */
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#endif /* STM32MP_DDR_DUAL_AXI_PORT */
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#define DDRPHY_REG_REG_SIZE 0 /* st,phy-reg */
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#define DDRPHY_REG_TIMING_SIZE 0 /* st,phy-timing */
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#define DDRCTL_REG_REG(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_reg, z)
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static const struct stm32mp_ddr_reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
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DDRCTL_REG_REG(mstr, true),
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DDRCTL_REG_REG(mrctrl0, false),
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DDRCTL_REG_REG(mrctrl1, false),
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DDRCTL_REG_REG(mrctrl2, false),
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DDRCTL_REG_REG(derateen, true),
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DDRCTL_REG_REG(derateint, false),
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DDRCTL_REG_REG(deratectl, false),
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DDRCTL_REG_REG(pwrctl, false),
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DDRCTL_REG_REG(pwrtmg, true),
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DDRCTL_REG_REG(hwlpctl, true),
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DDRCTL_REG_REG(rfshctl0, false),
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DDRCTL_REG_REG(rfshctl1, false),
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DDRCTL_REG_REG(rfshctl3, true),
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DDRCTL_REG_REG(crcparctl0, false),
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DDRCTL_REG_REG(crcparctl1, false),
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DDRCTL_REG_REG(init0, true),
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DDRCTL_REG_REG(init1, false),
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DDRCTL_REG_REG(init2, false),
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DDRCTL_REG_REG(init3, true),
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DDRCTL_REG_REG(init4, true),
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DDRCTL_REG_REG(init5, false),
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DDRCTL_REG_REG(init6, true),
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DDRCTL_REG_REG(init7, true),
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DDRCTL_REG_REG(dimmctl, false),
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DDRCTL_REG_REG(rankctl, true),
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DDRCTL_REG_REG(rankctl1, true),
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DDRCTL_REG_REG(zqctl0, true),
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DDRCTL_REG_REG(zqctl1, false),
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DDRCTL_REG_REG(zqctl2, false),
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DDRCTL_REG_REG(dfitmg0, true),
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DDRCTL_REG_REG(dfitmg1, true),
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DDRCTL_REG_REG(dfilpcfg0, false),
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DDRCTL_REG_REG(dfilpcfg1, false),
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DDRCTL_REG_REG(dfiupd0, true),
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DDRCTL_REG_REG(dfiupd1, false),
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DDRCTL_REG_REG(dfiupd2, false),
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DDRCTL_REG_REG(dfimisc, true),
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DDRCTL_REG_REG(dfitmg2, true),
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DDRCTL_REG_REG(dfitmg3, false),
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DDRCTL_REG_REG(dbictl, true),
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DDRCTL_REG_REG(dfiphymstr, false),
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DDRCTL_REG_REG(dbg0, false),
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DDRCTL_REG_REG(dbg1, false),
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DDRCTL_REG_REG(dbgcmd, false),
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DDRCTL_REG_REG(swctl, false), /* forced qd value */
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DDRCTL_REG_REG(swctlstatic, false),
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DDRCTL_REG_REG(poisoncfg, false),
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DDRCTL_REG_REG(pccfg, false),
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};
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#define DDRCTL_REG_TIMING(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_timing, z)
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static const struct stm32mp_ddr_reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
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DDRCTL_REG_TIMING(rfshtmg, false),
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DDRCTL_REG_TIMING(rfshtmg1, false),
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DDRCTL_REG_TIMING(dramtmg0, true),
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DDRCTL_REG_TIMING(dramtmg1, true),
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DDRCTL_REG_TIMING(dramtmg2, true),
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DDRCTL_REG_TIMING(dramtmg3, true),
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DDRCTL_REG_TIMING(dramtmg4, true),
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DDRCTL_REG_TIMING(dramtmg5, true),
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DDRCTL_REG_TIMING(dramtmg6, true),
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DDRCTL_REG_TIMING(dramtmg7, true),
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DDRCTL_REG_TIMING(dramtmg8, true),
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DDRCTL_REG_TIMING(dramtmg9, true),
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DDRCTL_REG_TIMING(dramtmg10, true),
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DDRCTL_REG_TIMING(dramtmg11, true),
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DDRCTL_REG_TIMING(dramtmg12, true),
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DDRCTL_REG_TIMING(dramtmg13, true),
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DDRCTL_REG_TIMING(dramtmg14, true),
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DDRCTL_REG_TIMING(dramtmg15, true),
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DDRCTL_REG_TIMING(odtcfg, true),
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DDRCTL_REG_TIMING(odtmap, false),
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};
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#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp2_ddrctrl_map, false)
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static const struct stm32mp_ddr_reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
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DDRCTL_REG_MAP(addrmap0),
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DDRCTL_REG_MAP(addrmap1),
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DDRCTL_REG_MAP(addrmap2),
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DDRCTL_REG_MAP(addrmap3),
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DDRCTL_REG_MAP(addrmap4),
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DDRCTL_REG_MAP(addrmap5),
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DDRCTL_REG_MAP(addrmap6),
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DDRCTL_REG_MAP(addrmap7),
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DDRCTL_REG_MAP(addrmap8),
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DDRCTL_REG_MAP(addrmap9),
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DDRCTL_REG_MAP(addrmap10),
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DDRCTL_REG_MAP(addrmap11),
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};
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#define DDRCTL_REG_PERF(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_perf, z)
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static const struct stm32mp_ddr_reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
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DDRCTL_REG_PERF(sched, true),
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DDRCTL_REG_PERF(sched1, false),
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DDRCTL_REG_PERF(perfhpr1, true),
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DDRCTL_REG_PERF(perflpr1, true),
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DDRCTL_REG_PERF(perfwr1, true),
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DDRCTL_REG_PERF(sched3, false),
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DDRCTL_REG_PERF(sched4, false),
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DDRCTL_REG_PERF(pcfgr_0, false),
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DDRCTL_REG_PERF(pcfgw_0, false),
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DDRCTL_REG_PERF(pctrl_0, false),
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DDRCTL_REG_PERF(pcfgqos0_0, true),
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DDRCTL_REG_PERF(pcfgqos1_0, true),
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DDRCTL_REG_PERF(pcfgwqos0_0, true),
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DDRCTL_REG_PERF(pcfgwqos1_0, true),
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#if STM32MP_DDR_DUAL_AXI_PORT
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DDRCTL_REG_PERF(pcfgr_1, false),
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DDRCTL_REG_PERF(pcfgw_1, false),
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DDRCTL_REG_PERF(pctrl_1, false),
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DDRCTL_REG_PERF(pcfgqos0_1, true),
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DDRCTL_REG_PERF(pcfgqos1_1, true),
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DDRCTL_REG_PERF(pcfgwqos0_1, true),
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DDRCTL_REG_PERF(pcfgwqos1_1, true),
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#endif /* STM32MP_DDR_DUAL_AXI_PORT */
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};
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static const struct stm32mp_ddr_reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {};
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static const struct stm32mp_ddr_reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {};
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/*
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* REGISTERS ARRAY: used to parse device tree and interactive mode
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*/
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static const struct stm32mp_ddr_reg_info ddr_registers[REG_TYPE_NB] __unused = {
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[REG_REG] = {
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.name = "static",
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.desc = ddr_reg,
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.size = DDRCTL_REG_REG_SIZE,
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.base = DDR_BASE
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},
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[REG_TIMING] = {
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.name = "timing",
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.desc = ddr_timing,
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.size = DDRCTL_REG_TIMING_SIZE,
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.base = DDR_BASE
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},
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[REG_PERF] = {
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.name = "perf",
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.desc = ddr_perf,
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.size = DDRCTL_REG_PERF_SIZE,
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.base = DDR_BASE
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},
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[REG_MAP] = {
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.name = "map",
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.desc = ddr_map,
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.size = DDRCTL_REG_MAP_SIZE,
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.base = DDR_BASE
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},
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[REGPHY_REG] = {
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.name = "static",
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.desc = ddrphy_reg,
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.size = DDRPHY_REG_REG_SIZE,
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.base = DDRPHY_BASE
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},
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[REGPHY_TIMING] = {
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.name = "timing",
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.desc = ddrphy_timing,
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.size = DDRPHY_REG_TIMING_SIZE,
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.base = DDRPHY_BASE
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},
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};
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static void ddr_reset(struct stm32mp_ddr_priv *priv)
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{
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udelay(DDR_DELAY_1US);
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mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
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mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
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RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN |
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RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
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mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
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RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN |
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RCC_DDRCAPBCFGR_DDRCAPBRST);
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mmio_write_32(priv->rcc + RCC_DDRCFGR,
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RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN | RCC_DDRCFGR_DDRCFGRST);
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udelay(DDR_DELAY_1US);
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mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
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mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
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RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN);
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mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
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RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN);
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mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);
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udelay(DDR_DELAY_1US);
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}
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static void ddr_standby_reset(struct stm32mp_ddr_priv *priv)
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{
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udelay(DDR_DELAY_1US);
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mmio_write_32(priv->rcc + RCC_DDRCPCFGR,
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RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPRST);
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mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
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mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
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RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN |
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RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
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mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
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RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN |
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RCC_DDRCAPBCFGR_DDRCAPBRST);
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mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
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mmio_setbits_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
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udelay(DDR_DELAY_1US);
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}
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static void ddr_standby_reset_release(struct stm32mp_ddr_priv *priv)
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{
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udelay(DDR_DELAY_1US);
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mmio_write_32(priv->rcc + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
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mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
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mmio_clrbits_32(priv->rcc + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
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mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);
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udelay(DDR_DELAY_1US);
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}
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static void ddr_sysconf_configuration(struct stm32mp_ddr_priv *priv,
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struct stm32mp_ddr_config *config)
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{
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mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE,
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DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE);
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mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_BYPASS_PCLKEN,
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(uint32_t)config->uib.pllbypass);
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mmio_write_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
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mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
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udelay(DDR_DELAY_1US);
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}
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static void set_dfi_init_complete_en(struct stm32mp_ddrctl *ctl, bool phy_init_done)
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{
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/*
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* Manage quasi-dynamic registers modification
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* dfimisc.dfi_init_complete_en : Group 3
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*/
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stm32mp_ddr_set_qd3_update_conditions(ctl);
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udelay(DDR_DELAY_1US);
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if (phy_init_done) {
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/* Indicates to controller that PHY has completed initialization */
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mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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} else {
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/* PHY not initialized yet, wait for completion */
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mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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}
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udelay(DDR_DELAY_1US);
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stm32mp_ddr_unset_qd3_update_conditions(ctl);
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}
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static void disable_refresh(struct stm32mp_ddrctl *ctl)
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{
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mmio_setbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
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stm32mp_ddr_wait_refresh_update_done_ack(ctl);
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udelay(DDR_DELAY_1US);
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mmio_clrbits_32((uintptr_t)&ctl->pwrctl,
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DDRCTRL_PWRCTL_POWERDOWN_EN | DDRCTRL_PWRCTL_SELFREF_EN);
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udelay(DDR_DELAY_1US);
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set_dfi_init_complete_en(ctl, false);
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}
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static void restore_refresh(struct stm32mp_ddrctl *ctl, uint32_t rfshctl3, uint32_t pwrctl)
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{
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if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) {
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mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
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stm32mp_ddr_wait_refresh_update_done_ack(ctl);
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udelay(DDR_DELAY_1US);
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}
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if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_SW) != 0U) {
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mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
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udelay(DDR_DELAY_1US);
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}
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if ((pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) != 0U) {
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mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
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udelay(DDR_DELAY_1US);
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}
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if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) != 0U) {
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mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
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udelay(DDR_DELAY_1US);
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}
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set_dfi_init_complete_en(ctl, true);
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}
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void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv,
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struct stm32mp_ddr_config *config)
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{
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int ret = -EINVAL;
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uint32_t ddr_retdis;
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enum ddr_type ddr_type;
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if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) {
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ddr_type = STM32MP_DDR3;
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} else if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR4) != 0U) {
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ddr_type = STM32MP_DDR4;
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} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR4) != 0U) {
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ddr_type = STM32MP_LPDDR4;
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} else {
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ERROR("DDR type not supported\n");
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panic();
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}
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VERBOSE("name = %s\n", config->info.name);
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VERBOSE("speed = %u kHz\n", config->info.speed);
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VERBOSE("size = 0x%zx\n", config->info.size);
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if (config->self_refresh) {
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VERBOSE("sel-refresh exit (zdata = 0x%x)\n", config->zdata);
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}
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/* Check DDR PHY pads retention */
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ddr_retdis = mmio_read_32(priv->pwr + PWR_CR11) & PWR_CR11_DDRRETDIS;
|
|
if (config->self_refresh) {
|
|
if (ddr_retdis == PWR_CR11_DDRRETDIS) {
|
|
VERBOSE("self-refresh aborted: no retention\n");
|
|
config->self_refresh = false;
|
|
}
|
|
}
|
|
|
|
if (config->self_refresh) {
|
|
ddr_standby_reset(priv);
|
|
|
|
VERBOSE("disable DDR PHY retention\n");
|
|
mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);
|
|
|
|
udelay(DDR_DELAY_1US);
|
|
|
|
mmio_clrbits_32(priv->rcc + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST);
|
|
|
|
udelay(DDR_DELAY_1US);
|
|
|
|
} else {
|
|
if (stm32mp_board_ddr_power_init(ddr_type) != 0) {
|
|
ERROR("DDR power init failed\n");
|
|
panic();
|
|
}
|
|
|
|
VERBOSE("disable DDR PHY retention\n");
|
|
mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);
|
|
|
|
ddr_reset(priv);
|
|
|
|
ddr_sysconf_configuration(priv, config);
|
|
}
|
|
|
|
#if STM32MP_LPDDR4_TYPE
|
|
/*
|
|
* Enable PWRCTL.SELFREF_SW to ensure correct setting of PWRCTL.LPDDR4_SR_ALLOWED.
|
|
* Later disabled in restore_refresh().
|
|
*/
|
|
config->c_reg.pwrctl |= DDRCTRL_PWRCTL_SELFREF_SW;
|
|
#endif /* STM32MP_LPDDR4_TYPE */
|
|
|
|
stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers);
|
|
stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers);
|
|
stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers);
|
|
stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers);
|
|
|
|
if (!config->self_refresh) {
|
|
/* DDR core and PHY reset de-assert */
|
|
mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
|
|
|
|
disable_refresh(priv->ctl);
|
|
}
|
|
|
|
if (config->self_refresh) {
|
|
ddr_standby_reset_release(priv);
|
|
|
|
/* Initialize DDR by skipping training and disabling result saving */
|
|
ret = ddrphy_phyinit_sequence(config, true, false);
|
|
|
|
if (ret == 0) {
|
|
ret = ddrphy_phyinit_restore_sequence();
|
|
}
|
|
|
|
/* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */
|
|
ddr_wait_lp3_mode(false);
|
|
} else {
|
|
/* Initialize DDR including training and result saving */
|
|
ret = ddrphy_phyinit_sequence(config, false, true);
|
|
}
|
|
|
|
if (ret != 0) {
|
|
ERROR("DDR PHY init: Error %d\n", ret);
|
|
panic();
|
|
}
|
|
|
|
ddr_activate_controller(priv->ctl, false);
|
|
|
|
if (config->self_refresh) {
|
|
struct stm32mp_ddrctl *ctl = priv->ctl;
|
|
|
|
/* SW self refresh exit prequested */
|
|
mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
|
|
|
|
if (ddr_sr_exit_loop() != 0) {
|
|
ERROR("DDR Standby exit error\n");
|
|
panic();
|
|
}
|
|
|
|
/* Re-enable DFI low-power interface */
|
|
mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
|
|
} else {
|
|
restore_refresh(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl);
|
|
}
|
|
|
|
stm32mp_ddr_enable_axi_port(priv->ctl);
|
|
}
|