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https://github.com/ARM-software/arm-trusted-firmware.git
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f4db9216f5
Add QoS support for RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: If541278fd629761cc83398bba71e63f09d9dbee6
210 lines
7.1 KiB
C
210 lines
7.1 KiB
C
/*
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* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "../qos_common.h"
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#include "qos_init_g2m_v30.h"
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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#include "qos_init_g2m_v30_mstat195.h"
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#else /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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#include "qos_init_g2m_v30_mstat390.h"
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#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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#include "qos_init_g2m_v30_qoswt195.h"
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#else /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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#include "qos_init_g2m_v30_qoswt390.h"
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#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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#endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */
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#include "qos_reg.h"
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#define RCAR_QOS_VERSION "rev.0.04"
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#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
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#define QOSWT_WTEN_ENABLE 0x1U
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#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2M_30 (SL_INIT_SSLOTCLK_G2M_30 - 0x5U)
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#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
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#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
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#define QOSWT_WTREF_SLOT0_EN \
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((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
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(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
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#define QOSWT_WTREF_SLOT1_EN \
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((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
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(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
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#define QOSWT_WTSET0_REQ_SSLOT0 5U
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#define WT_BASE_SUB_SLOT_NUM0 12U
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#define QOSWT_WTSET0_PERIOD0_G2M_30 \
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((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2M_30) - 1U)
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#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
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#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
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#define QOSWT_WTSET1_PERIOD1_G2M_30 \
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((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2M_30) - 1U)
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#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
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#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
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static const struct rcar_gen3_dbsc_qos_settings g2m_v30_qos[] = {
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/* BUFCAM settings */
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{ DBSC_DBCAM0CNF1, 0x00043218U },
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{ DBSC_DBCAM0CNF2, 0x000000F4U },
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{ DBSC_DBCAM0CNF3, 0x00000000U },
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{ DBSC_DBSCHCNT0, 0x000F0037U },
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{ DBSC_DBSCHSZ0, 0x00000001U },
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{ DBSC_DBSCHRW0, 0x22421111U },
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/* DDR3 */
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{ DBSC_SCFCTST2, 0x012F1123U },
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/* QoS settings */
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{ DBSC_DBSCHQOS00, 0x00000F00U },
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{ DBSC_DBSCHQOS01, 0x00000B00U },
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{ DBSC_DBSCHQOS02, 0x00000000U },
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{ DBSC_DBSCHQOS03, 0x00000000U },
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{ DBSC_DBSCHQOS40, 0x00000300U },
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{ DBSC_DBSCHQOS41, 0x000002F0U },
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{ DBSC_DBSCHQOS42, 0x00000200U },
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{ DBSC_DBSCHQOS43, 0x00000100U },
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{ DBSC_DBSCHQOS90, 0x00000100U },
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{ DBSC_DBSCHQOS91, 0x000000F0U },
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{ DBSC_DBSCHQOS92, 0x000000A0U },
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{ DBSC_DBSCHQOS93, 0x00000040U },
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{ DBSC_DBSCHQOS120, 0x00000040U },
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{ DBSC_DBSCHQOS121, 0x00000030U },
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{ DBSC_DBSCHQOS122, 0x00000020U },
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{ DBSC_DBSCHQOS123, 0x00000010U },
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{ DBSC_DBSCHQOS130, 0x00000100U },
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{ DBSC_DBSCHQOS131, 0x000000F0U },
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{ DBSC_DBSCHQOS132, 0x000000A0U },
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{ DBSC_DBSCHQOS133, 0x00000040U },
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{ DBSC_DBSCHQOS140, 0x000000C0U },
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{ DBSC_DBSCHQOS141, 0x000000B0U },
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{ DBSC_DBSCHQOS142, 0x00000080U },
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{ DBSC_DBSCHQOS143, 0x00000040U },
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{ DBSC_DBSCHQOS150, 0x00000040U },
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{ DBSC_DBSCHQOS151, 0x00000030U },
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{ DBSC_DBSCHQOS152, 0x00000020U },
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{ DBSC_DBSCHQOS153, 0x00000010U },
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};
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void qos_init_g2m_v30(void)
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{
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uint32_t i;
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rzg_qos_dbsc_setting(g2m_v30_qos, ARRAY_SIZE(g2m_v30_qos), true);
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/* DRAM Split Address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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#if RCAR_LSI == RZ_G2M
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#error "Don't set DRAM Split 4ch(G2M)"
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#else /* RCAR_LSI == RZ_G2M */
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ERROR("DRAM Split 4ch not supported.(G2M)");
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panic();
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#endif /* RCAR_LSI == RZ_G2M */
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#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
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(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
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NOTICE("BL2: DRAM Split is 2ch\n");
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mmio_write_32(AXI_ADSPLCR0, 0x00000000U);
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mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
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ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(0x1DU) |
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ADSPLCR0_SWP);
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mmio_write_32(AXI_ADSPLCR2, 0x00001004U);
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mmio_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
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NOTICE("BL2: DRAM Split is OFF\n");
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#endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
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#else /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
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#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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NOTICE("BL2: Periodic Write DQ Training\n");
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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mmio_write_32(QOSCTRL_RAS, 0x00000044U);
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mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
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mmio_write_32(QOSCTRL_DANT, 0x0020100AU);
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mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
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mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
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mmio_write_32(QOSCTRL_EARLYR, 0x00000001U);
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mmio_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
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/* GPU Boost Mode */
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mmio_write_32(QOSCTRL_STATGEN0, 0x00000001U);
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mmio_write_32(QOSCTRL_SL_INIT,
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SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
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SL_INIT_SSLOTCLK_G2M_30);
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mmio_write_32(QOSCTRL_REF_ARS,
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QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2M_30 << 16);
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
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mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
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mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
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}
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
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mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
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mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
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mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
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mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
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}
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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/* RT bus Leaf setting */
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mmio_write_32(RT_ACT0, 0x00000000U);
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mmio_write_32(RT_ACT1, 0x00000000U);
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/* CCI bus Leaf setting */
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mmio_write_32(CPU_ACT0, 0x00000003U);
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mmio_write_32(CPU_ACT1, 0x00000003U);
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mmio_write_32(CPU_ACT2, 0x00000003U);
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mmio_write_32(CPU_ACT3, 0x00000003U);
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mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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/* re-write training setting */
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mmio_write_32(QOSWT_WTREF,
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(QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN);
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mmio_write_32(QOSWT_WTSET0, (QOSWT_WTSET0_PERIOD0_G2M_30 << 16) |
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(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0);
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mmio_write_32(QOSWT_WTSET1, (QOSWT_WTSET1_PERIOD1_G2M_30 << 16) |
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(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1);
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mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
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#else /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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NOTICE("BL2: QoS is None\n");
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mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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