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https://github.com/ARM-software/arm-trusted-firmware.git
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f4db9216f5
Add QoS support for RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: If541278fd629761cc83398bba71e63f09d9dbee6
148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
/*
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* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "../qos_common.h"
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#include "qos_init_g2m_v10.h"
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#include "qos_init_g2m_v10_mstat.h"
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#include "qos_reg.h"
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#define RCAR_QOS_VERSION "rev.0.19"
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static const struct rcar_gen3_dbsc_qos_settings g2m_v10_qos[] = {
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/* BUFCAM settings */
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/* DBSC_DBCAM0CNF0 not set */
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{ DBSC_DBCAM0CNF1, 0x00043218U },
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{ DBSC_DBCAM0CNF2, 0x000000F4U },
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{ DBSC_DBCAM0CNF3, 0x00000000U },
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{ DBSC_DBSCHCNT0, 0x080F0037U },
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/* DBSC_DBSCHCNT1 not set */
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{ DBSC_DBSCHSZ0, 0x00000001U },
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{ DBSC_DBSCHRW0, 0x22421111U },
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/* DDR3 */
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{ DBSC_SCFCTST2, 0x012F1123U },
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/* QoS Settings */
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{ DBSC_DBSCHQOS00, 0x00000F00U },
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{ DBSC_DBSCHQOS01, 0x00000B00U },
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{ DBSC_DBSCHQOS02, 0x00000000U },
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{ DBSC_DBSCHQOS03, 0x00000000U },
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{ DBSC_DBSCHQOS40, 0x00000300U },
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{ DBSC_DBSCHQOS41, 0x000002F0U },
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{ DBSC_DBSCHQOS42, 0x00000200U },
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{ DBSC_DBSCHQOS43, 0x00000100U },
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{ DBSC_DBSCHQOS90, 0x00000300U },
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{ DBSC_DBSCHQOS91, 0x000002F0U },
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{ DBSC_DBSCHQOS92, 0x00000200U },
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{ DBSC_DBSCHQOS93, 0x00000100U },
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{ DBSC_DBSCHQOS130, 0x00000100U },
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{ DBSC_DBSCHQOS131, 0x000000F0U },
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{ DBSC_DBSCHQOS132, 0x000000A0U },
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{ DBSC_DBSCHQOS133, 0x00000040U },
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{ DBSC_DBSCHQOS140, 0x000000C0U },
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{ DBSC_DBSCHQOS141, 0x000000B0U },
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{ DBSC_DBSCHQOS142, 0x00000080U },
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{ DBSC_DBSCHQOS143, 0x00000040U },
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{ DBSC_DBSCHQOS150, 0x00000040U },
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{ DBSC_DBSCHQOS151, 0x00000030U },
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{ DBSC_DBSCHQOS152, 0x00000020U },
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{ DBSC_DBSCHQOS153, 0x00000010U },
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};
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void qos_init_g2m_v10(void)
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{
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rzg_qos_dbsc_setting(g2m_v10_qos, ARRAY_SIZE(g2m_v10_qos), false);
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/* DRAM split address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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#if RCAR_LSI == RZ_G2M
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#error "Don't set DRAM Split 4ch(G2M)"
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#else /* RCAR_LSI == RZ_G2M */
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ERROR("DRAM Split 4ch not supported.(G2M)");
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panic();
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#endif /* RCAR_LSI == RZ_G2M */
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#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
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(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
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NOTICE("BL2: DRAM Split is 2ch\n");
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mmio_write_32(AXI_ADSPLCR0, 0x00000000U);
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mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
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ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(0x1CU) |
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ADSPLCR0_SWP);
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mmio_write_32(AXI_ADSPLCR2, 0x089A0000U);
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mmio_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
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NOTICE("BL2: DRAM Split is OFF\n");
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#endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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/* Resource Alloc setting */
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mmio_write_32(QOSCTRL_RAS, 0x00000028U);
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mmio_write_32(QOSCTRL_FIXTH, 0x000F0005U);
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mmio_write_32(QOSCTRL_REGGD, 0x00000000U);
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mmio_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
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mmio_write_32(QOSCTRL_DANT, 0x00100804U);
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mmio_write_32(QOSCTRL_EC, 0x00000000U);
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mmio_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
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mmio_write_32(QOSCTRL_FSS, 0x000003e8U);
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mmio_write_32(QOSCTRL_INSFC, 0xC7840001U);
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mmio_write_32(QOSCTRL_BERR, 0x00000000U);
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mmio_write_32(QOSCTRL_RACNT0, 0x00000000U);
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/* QOSBW setting */
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mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
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SL_INIT_SSLOTCLK);
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mmio_write_32(QOSCTRL_REF_ARS, 0x00330000U);
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/* QOSBW SRAM setting */
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
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mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
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mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
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}
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/* 3DG bus Leaf setting */
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mmio_write_32(0xFD820808U, 0x00001234U);
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mmio_write_32(0xFD820800U, 0x00000006U);
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mmio_write_32(0xFD821800U, 0x00000006U);
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mmio_write_32(0xFD822800U, 0x00000006U);
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mmio_write_32(0xFD823800U, 0x00000006U);
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mmio_write_32(0xFD824800U, 0x00000006U);
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mmio_write_32(0xFD825800U, 0x00000006U);
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mmio_write_32(0xFD826800U, 0x00000006U);
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mmio_write_32(0xFD827800U, 0x00000006U);
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/* RT bus Leaf setting */
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mmio_write_32(0xFFC50800U, 0x00000000U);
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mmio_write_32(0xFFC51800U, 0x00000000U);
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/* Resource Alloc start */
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mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
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/* QOSBW start */
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mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
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#else /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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NOTICE("BL2: QoS is None\n");
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/* Resource Alloc setting */
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mmio_write_32(QOSCTRL_EC, 0x00000000U);
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/* Resource Alloc start */
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mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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