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11a7c54072
MC_RGM is a hardware block involved in resetting peripherals and partitions. Here, the accessories for partition reset are added. Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* Copyright 2023-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <s32cc-mc-rgm.h>
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#define MC_RGM_PRST(RGM, PER) ((RGM) + 0x40UL + ((PER) * 0x8UL))
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#define MC_RGM_PRST_PERIPH_N_RST(PER) BIT_32(PER)
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#define MC_RGM_PSTAT(RGM, PER) ((RGM) + 0x140UL + ((PER) * 0x8UL))
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#define MC_RGM_PSTAT_PERIPH(PER) BIT_32(PER)
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/* ERR051700
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* Releasing more than one Software Resettable Domain (SRD)
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* from reset simultaneously, by clearing the corresponding
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* peripheral MC_RGM_PRSTn[PERIPH_x_RST] reset control may
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* cause a false setting of the Fault Collection and
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* Control Unit (FCCU) Non-Critical Fault (NCF) flag
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* corresponding to a Memory-Test-Repair (MTR) Error
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*/
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#if (ERRATA_S32_051700 == 1)
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void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
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{
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uint32_t current_bit_checked, i;
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uint32_t current_regs, mask;
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int bit_index;
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current_regs = mmio_read_32(MC_RGM_PRST(rgm, part));
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/* Create a mask with all changed bits */
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mask = current_regs ^ value;
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while (mask != 0U) {
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bit_index = __builtin_ffs(mask);
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if (bit_index < 1) {
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break;
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}
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i = (uint32_t)bit_index - 1U;
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current_bit_checked = BIT_32(i);
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/* Check if we assert or de-assert.
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* Also wait for completion.
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*/
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if ((value & current_bit_checked) != 0U) {
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mmio_setbits_32(MC_RGM_PRST(rgm, part),
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current_bit_checked);
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while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
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current_bit_checked) == 0U)
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;
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} else {
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mmio_clrbits_32(MC_RGM_PRST(rgm, part),
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current_bit_checked);
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while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
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current_bit_checked) != 0U)
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;
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}
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mask &= ~current_bit_checked;
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}
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}
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#else /* ERRATA_S32_051700 */
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void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
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{
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mmio_write_32(MC_RGM_PRST(rgm, part), value);
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}
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#endif /* ERRATA_S32_051700 */
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void mc_rgm_release_part(uintptr_t rgm, uint32_t part)
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{
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uint32_t reg;
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reg = mmio_read_32(MC_RGM_PRST(rgm, part));
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reg &= ~MC_RGM_PRST_PERIPH_N_RST(0);
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mc_rgm_periph_reset(rgm, part, reg);
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}
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void mc_rgm_wait_part_deassert(uintptr_t rgm, uint32_t part)
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{
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while ((mmio_read_32(MC_RGM_PSTAT(rgm, part)) &
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MC_RGM_PSTAT_PERIPH(0)) != 0U) {
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}
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}
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