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81c2a044e2
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
22 lines
651 B
C
22 lines
651 B
C
/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* DFX sub-FID */
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#define MV_SIP_DFX_THERMAL_INIT 1
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#define MV_SIP_DFX_THERMAL_READ 2
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#define MV_SIP_DFX_THERMAL_IS_VALID 3
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#define MV_SIP_DFX_THERMAL_IRQ 4
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#define MV_SIP_DFX_THERMAL_THRESH 5
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#define MV_SIP_DFX_THERMAL_SEL_CHANNEL 6
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#define MV_SIP_DFX_SREAD 20
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#define MV_SIP_DFX_SWRITE 21
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int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
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u_register_t x2, u_register_t x3);
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int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
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u_register_t addr, u_register_t val);
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