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b81444e843
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
15 lines
401 B
C
15 lines
401 B
C
/*
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <plat_marvell.h>
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#define DEVICE_BASE 0xF0000000
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#define DDR_PHY_OFFSET 0x1000000
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#define DDR_PHY_BASE_ADDR (DEVICE_BASE + DDR_PHY_OFFSET)
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int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data);
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int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read);
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