mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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af26d7d6f0
The Arm Message Handling Unit (MHU) is a mailbox controller used to communicate with other processing element(s). Adding a driver to enable the communication: - Adding generic MHU driver interface, - Adding MHU_v2_x driver. Driver supports: - Discovering available MHU channels, - Sending / receiving words over MHU channels, - Signaling happens over a dedicated channel. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Signed-off-by: David Vincze <david.vincze@arm.com> Change-Id: I41a5b968f6b8319cdbdf7907d70bd8837839862e
379 lines
9.9 KiB
C
379 lines
9.9 KiB
C
/*
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "mhu_v2_x.h"
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#define MHU_V2_X_MAX_CHANNELS 124
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#define MHU_V2_1_MAX_CHCOMB_INT 4
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#define ENABLE 0x1
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#define DISABLE 0x0
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#define CLEAR_INTR 0x1
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#define CH_PER_CH_COMB 0x20
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#define SEND_FRAME(p_mhu) ((struct mhu_v2_x_send_frame_t *)p_mhu)
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#define RECV_FRAME(p_mhu) ((struct mhu_v2_x_recv_frame_t *)p_mhu)
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#define MHU_MAJOR_REV_V2 0x1u
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#define MHU_MINOR_REV_2_0 0x0u
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#define MHU_MINOR_REV_2_1 0x1u
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struct mhu_v2_x_send_ch_window_t {
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/* Offset: 0x00 (R/ ) Channel Status */
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volatile uint32_t ch_st;
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/* Offset: 0x04 (R/ ) Reserved */
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volatile uint32_t reserved_0;
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/* Offset: 0x08 (R/ ) Reserved */
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volatile uint32_t reserved_1;
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/* Offset: 0x0C ( /W) Channel Set */
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volatile uint32_t ch_set;
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/* Offset: 0x10 (R/ ) Channel Interrupt Status (Reserved in 2.0) */
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volatile uint32_t ch_int_st;
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/* Offset: 0x14 ( /W) Channel Interrupt Clear (Reserved in 2.0) */
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volatile uint32_t ch_int_clr;
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/* Offset: 0x18 (R/W) Channel Interrupt Enable (Reserved in 2.0) */
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volatile uint32_t ch_int_en;
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/* Offset: 0x1C (R/ ) Reserved */
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volatile uint32_t reserved_2;
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};
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struct mhu_v2_x_send_frame_t {
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/* Offset: 0x000 ( / ) Sender Channel Window 0 -123 */
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struct mhu_v2_x_send_ch_window_t send_ch_window[MHU_V2_X_MAX_CHANNELS];
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/* Offset: 0xF80 (R/ ) Message Handling Unit Configuration */
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volatile uint32_t mhu_cfg;
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/* Offset: 0xF84 (R/W) Response Configuration */
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volatile uint32_t resp_cfg;
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/* Offset: 0xF88 (R/W) Access Request */
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volatile uint32_t access_request;
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/* Offset: 0xF8C (R/ ) Access Ready */
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volatile uint32_t access_ready;
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/* Offset: 0xF90 (R/ ) Interrupt Status */
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volatile uint32_t int_st;
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/* Offset: 0xF94 ( /W) Interrupt Clear */
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volatile uint32_t int_clr;
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/* Offset: 0xF98 (R/W) Interrupt Enable */
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volatile uint32_t int_en;
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/* Offset: 0xF9C (R/ ) Reserved */
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volatile uint32_t reserved_0;
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/* Offset: 0xFA0 (R/W) Channel Combined IRQ Stat (Reserved in 2.0) */
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volatile uint32_t ch_comb_int_st[MHU_V2_1_MAX_CHCOMB_INT];
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/* Offset: 0xFC4 (R/ ) Reserved */
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volatile uint32_t reserved_1[6];
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/* Offset: 0xFC8 (R/ ) Implementer Identification Register */
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volatile uint32_t iidr;
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/* Offset: 0xFCC (R/ ) Architecture Identification Register */
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volatile uint32_t aidr;
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/* Offset: 0xFD0 (R/ ) */
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volatile uint32_t pid_1[4];
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/* Offset: 0xFE0 (R/ ) */
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volatile uint32_t pid_0[4];
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/* Offset: 0xFF0 (R/ ) */
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volatile uint32_t cid[4];
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};
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struct mhu_v2_x_rec_ch_window_t {
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/* Offset: 0x00 (R/ ) Channel Status */
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volatile uint32_t ch_st;
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/* Offset: 0x04 (R/ ) Channel Status Masked */
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volatile uint32_t ch_st_msk;
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/* Offset: 0x08 ( /W) Channel Clear */
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volatile uint32_t ch_clr;
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/* Offset: 0x0C (R/ ) Reserved */
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volatile uint32_t reserved_0;
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/* Offset: 0x10 (R/ ) Channel Mask Status */
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volatile uint32_t ch_msk_st;
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/* Offset: 0x14 ( /W) Channel Mask Set */
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volatile uint32_t ch_msk_set;
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/* Offset: 0x18 ( /W) Channel Mask Clear */
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volatile uint32_t ch_msk_clr;
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/* Offset: 0x1C (R/ ) Reserved */
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volatile uint32_t reserved_1;
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};
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struct mhu_v2_x_recv_frame_t {
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/* Offset: 0x000 ( / ) Receiver Channel Window 0 -123 */
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struct mhu_v2_x_rec_ch_window_t rec_ch_window[MHU_V2_X_MAX_CHANNELS];
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/* Offset: 0xF80 (R/ ) Message Handling Unit Configuration */
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volatile uint32_t mhu_cfg;
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/* Offset: 0xF84 (R/ ) Reserved */
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volatile uint32_t reserved_0[3];
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/* Offset: 0xF90 (R/ ) Interrupt Status (Reserved in 2.0) */
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volatile uint32_t int_st;
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/* Offset: 0xF94 (R/ ) Interrupt Clear (Reserved in 2.0) */
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volatile uint32_t int_clr;
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/* Offset: 0xF98 (R/W) Interrupt Enable (Reserved in 2.0) */
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volatile uint32_t int_en;
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/* Offset: 0xF9C (R/ ) Reserved */
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volatile uint32_t reserved_1;
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/* Offset: 0xFA0 (R/ ) Channel Combined IRQ Stat (Reserved in 2.0) */
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volatile uint32_t ch_comb_int_st[MHU_V2_1_MAX_CHCOMB_INT];
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/* Offset: 0xFB0 (R/ ) Reserved */
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volatile uint32_t reserved_2[6];
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/* Offset: 0xFC8 (R/ ) Implementer Identification Register */
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volatile uint32_t iidr;
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/* Offset: 0xFCC (R/ ) Architecture Identification Register */
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volatile uint32_t aidr;
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/* Offset: 0xFD0 (R/ ) */
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volatile uint32_t pid_1[4];
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/* Offset: 0xFE0 (R/ ) */
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volatile uint32_t pid_0[4];
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/* Offset: 0xFF0 (R/ ) */
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volatile uint32_t cid[4];
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};
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union mhu_v2_x_frame {
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struct mhu_v2_x_send_frame_t send_frame;
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struct mhu_v2_x_recv_frame_t recv_frame;
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};
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enum mhu_v2_x_error_t mhu_v2_x_driver_init(struct mhu_v2_x_dev_t *dev,
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enum mhu_v2_x_supported_revisions rev)
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{
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uint32_t AIDR = 0;
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (dev->is_initialized) {
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return MHU_V_2_X_ERR_ALREADY_INIT;
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}
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if (rev == MHU_REV_READ_FROM_HW) {
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/* Read revision from HW */
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if (dev->frame == MHU_V2_X_RECEIVER_FRAME) {
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AIDR = p_mhu->recv_frame.aidr;
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} else {
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AIDR = p_mhu->send_frame.aidr;
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}
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/* Get bits 7:4 to read major revision */
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if (((AIDR >> 4) & 0b1111) != MHU_MAJOR_REV_V2) {
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/* Unsupported MHU version */
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return MHU_V_2_X_ERR_UNSUPPORTED_VERSION;
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} /* No need to save major version, driver only supports MHUv2 */
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/* Get bits 3:0 to read minor revision */
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dev->subversion = AIDR & 0b1111;
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if (dev->subversion != MHU_MINOR_REV_2_0 &&
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dev->subversion != MHU_MINOR_REV_2_1) {
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/* Unsupported subversion */
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return MHU_V_2_X_ERR_UNSUPPORTED_VERSION;
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}
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} else {
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/* Revisions were provided by caller */
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if (rev == MHU_REV_2_0) {
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dev->subversion = MHU_MINOR_REV_2_0;
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} else if (rev == MHU_REV_2_1) {
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dev->subversion = MHU_MINOR_REV_2_1;
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} else {
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/* Unsupported subversion */
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return MHU_V_2_X_ERR_UNSUPPORTED_VERSION;
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} /* No need to save major version, driver only supports MHUv2 */
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}
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dev->is_initialized = true;
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return MHU_V_2_X_ERR_NONE;
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}
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uint32_t mhu_v2_x_get_num_channel_implemented(const struct mhu_v2_x_dev_t *dev)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_SENDER_FRAME) {
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return (SEND_FRAME(p_mhu))->mhu_cfg;
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} else {
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assert(dev->frame == MHU_V2_X_RECEIVER_FRAME);
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return (RECV_FRAME(p_mhu))->mhu_cfg;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_send(const struct mhu_v2_x_dev_t *dev,
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uint32_t channel, uint32_t val)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_SENDER_FRAME) {
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(SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_poll(const struct mhu_v2_x_dev_t *dev,
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uint32_t channel, uint32_t *value)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_SENDER_FRAME) {
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*value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_clear(const struct mhu_v2_x_dev_t *dev,
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uint32_t channel)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_RECEIVER_FRAME) {
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(RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_receive(
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const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_RECEIVER_FRAME) {
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*value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_mask_set(
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const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_RECEIVER_FRAME) {
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(RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_channel_mask_clear(
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const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame == MHU_V2_X_RECEIVER_FRAME) {
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(RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_clr = mask;
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return MHU_V_2_X_ERR_NONE;
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} else {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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}
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enum mhu_v2_x_error_t mhu_v2_x_initiate_transfer(
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const struct mhu_v2_x_dev_t *dev)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame != MHU_V2_X_SENDER_FRAME) {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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(SEND_FRAME(p_mhu))->access_request = ENABLE;
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while (!((SEND_FRAME(p_mhu))->access_ready)) {
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/* Wait in a loop for access ready signal to be high */
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;
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}
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return MHU_V_2_X_ERR_NONE;
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}
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enum mhu_v2_x_error_t mhu_v2_x_close_transfer(const struct mhu_v2_x_dev_t *dev)
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{
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union mhu_v2_x_frame *p_mhu;
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assert(dev != NULL);
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p_mhu = (union mhu_v2_x_frame *)dev->base;
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if (!(dev->is_initialized)) {
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return MHU_V_2_X_ERR_NOT_INIT;
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}
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if (dev->frame != MHU_V2_X_SENDER_FRAME) {
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return MHU_V_2_X_ERR_INVALID_ARG;
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}
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(SEND_FRAME(p_mhu))->access_request = DISABLE;
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return MHU_V_2_X_ERR_NONE;
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}
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