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https://github.com/ARM-software/arm-trusted-firmware.git
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c97857dba2
New SoC is a78 based with gicv3 and uart over pl011. Communication interfaces are similar to Versal NET platform. System starts with AMD PLM firmware which loads TF-A(bl31) to memory, which is already configured, and jumps to it. PLM also prepare handoff structure for TF-A with information what components were load and flags which indicate which EL level SW should be started. Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c Signed-off-by: Amit Nagal <amit.nagal@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
140 lines
3.1 KiB
C
140 lines
3.1 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Macros IDs for AMD Versal Gen 2
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*
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* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#ifndef _VERSAL2_SCMI_H
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#define _VERSAL2_SCMI_H
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#define CLK_GEM0_0 0
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#define CLK_GEM0_1 1
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#define CLK_GEM0_2 2
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#define CLK_GEM0_3 3
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#define CLK_GEM0_4 4
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#define CLK_GEM1_0 5
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#define CLK_GEM1_1 6
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#define CLK_GEM1_2 7
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#define CLK_GEM1_3 8
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#define CLK_GEM1_4 9
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#define CLK_SERIAL0_0 10
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#define CLK_SERIAL0_1 11
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#define CLK_SERIAL1_0 12
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#define CLK_SERIAL1_1 13
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#define CLK_UFS0_0 14
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#define CLK_UFS0_1 15
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#define CLK_UFS0_2 16
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#define CLK_USB0_0 17
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#define CLK_USB0_1 18
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#define CLK_USB0_2 19
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#define CLK_USB1_0 20
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#define CLK_USB1_1 21
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#define CLK_USB1_2 22
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#define CLK_MMC0_0 23
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#define CLK_MMC0_1 24
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#define CLK_MMC0_2 25
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#define CLK_MMC1_0 26
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#define CLK_MMC1_1 27
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#define CLK_MMC1_2 28
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#define CLK_TTC0_0 29
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#define CLK_TTC1_0 30
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#define CLK_TTC2_0 31
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#define CLK_TTC3_0 32
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#define CLK_TTC4_0 33
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#define CLK_TTC5_0 34
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#define CLK_TTC6_0 35
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#define CLK_TTC7_0 36
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#define CLK_I2C0_0 37
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#define CLK_I2C1_0 38
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#define CLK_I2C2_0 39
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#define CLK_I2C3_0 40
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#define CLK_I2C4_0 41
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#define CLK_I2C5_0 42
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#define CLK_I2C6_0 43
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#define CLK_I2C7_0 44
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#define CLK_OSPI0_0 45
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#define CLK_QSPI0_0 46
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#define CLK_QSPI0_1 47
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#define CLK_WWDT0_0 48
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#define CLK_WWDT1_0 49
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#define CLK_WWDT2_0 50
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#define CLK_WWDT3_0 51
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#define CLK_ADMA0_0 52
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#define CLK_ADMA0_1 53
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#define CLK_ADMA1_0 54
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#define CLK_ADMA1_1 55
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#define CLK_ADMA2_0 56
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#define CLK_ADMA2_1 57
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#define CLK_ADMA3_0 58
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#define CLK_ADMA3_1 59
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#define CLK_ADMA4_0 60
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#define CLK_ADMA4_1 61
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#define CLK_ADMA5_0 62
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#define CLK_ADMA5_1 63
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#define CLK_ADMA6_0 64
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#define CLK_ADMA6_1 65
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#define CLK_ADMA7_0 66
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#define CLK_ADMA7_1 67
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#define CLK_CAN0_0 68
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#define CLK_CAN0_1 69
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#define CLK_CAN1_0 70
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#define CLK_CAN1_1 71
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#define CLK_CAN2_0 72
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#define CLK_CAN2_1 73
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#define CLK_CAN3_0 74
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#define CLK_CAN3_1 75
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#define CLK_PS_GPIO_0 76
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#define CLK_PMC_GPIO_0 77
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#define CLK_SPI0_0 78
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#define CLK_SPI0_1 79
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#define CLK_SPI1_0 80
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#define CLK_SPI1_1 81
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#define CLK_I3C0_0 82
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#define CLK_I3C1_0 83
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#define CLK_I3C2_0 84
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#define CLK_I3C3_0 85
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#define CLK_I3C4_0 86
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#define CLK_I3C5_0 87
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#define CLK_I3C6_0 88
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#define CLK_I3C7_0 89
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#define RESET_GEM0_0 0
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#define RESET_GEM1_0 1
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#define RESET_SERIAL0_0 2
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#define RESET_SERIAL1_0 3
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#define RESET_UFS0_0 4
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#define RESET_I2C0_0 5
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#define RESET_I2C1_0 6
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#define RESET_I2C2_0 7
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#define RESET_I2C3_0 8
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#define RESET_I2C4_0 9
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#define RESET_I2C5_0 10
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#define RESET_I2C6_0 11
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#define RESET_I2C7_0 12
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#define RESET_I2C8_0 13
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#define RESET_OSPI0_0 14
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#define RESET_USB0_0 15
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#define RESET_USB0_1 16
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#define RESET_USB0_2 17
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#define RESET_USB1_0 18
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#define RESET_USB1_1 19
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#define RESET_USB1_2 20
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#define RESET_MMC0_0 21
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#define RESET_MMC1_0 22
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#define RESET_SPI0_0 23
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#define RESET_SPI1_0 24
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#define RESET_QSPI0_0 25
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#define RESET_I3C0_0 26
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#define RESET_I3C1_0 27
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#define RESET_I3C2_0 28
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#define RESET_I3C3_0 29
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#define RESET_I3C4_0 30
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#define RESET_I3C5_0 31
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#define RESET_I3C6_0 32
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#define RESET_I3C7_0 33
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#define RESET_I3C8_0 34
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#endif /* _VERSAL2_SCMI_H */
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