mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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0dae56bb2f
This commit deletes the value of the redefined CPG register. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
142 lines
5.2 KiB
C
142 lines
5.2 KiB
C
/*
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* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPG_REGISTERS_H
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#define CPG_REGISTERS_H
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/* CPG base address */
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#define CPG_BASE (0xE6150000U)
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/* CPG system module stop control 2 */
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#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U)
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/* CPG software reset 2 */
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#define CPG_SRCR2 (CPG_BASE + 0x00B0U)
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/* CPG module stop status 2 */
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#define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
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/* CPG module stop status 2 */
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#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
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/* CPG write protect */
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#define CPG_CPGWPR (CPG_BASE + 0x0900U)
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/* CPG write protect control */
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#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
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/* CPG system module stop control 9 */
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#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)
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/* CPG module stop status 9 */
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#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)
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/* SDHI2 clock frequency control register */
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#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
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/* SDHI3 clock frequency control register */
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#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
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/* CPG (SECURITY) registers */
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/* Secure Module Stop Control Register 0 */
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#define SCMSTPCR0 (CPG_BASE + 0x0B20U)
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/* Secure Module Stop Control Register 1 */
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#define SCMSTPCR1 (CPG_BASE + 0x0B24U)
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/* Secure Module Stop Control Register 2 */
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#define SCMSTPCR2 (CPG_BASE + 0x0B28U)
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/* Secure Module Stop Control Register 3 */
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#define SCMSTPCR3 (CPG_BASE + 0x0B2CU)
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/* Secure Module Stop Control Register 4 */
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#define SCMSTPCR4 (CPG_BASE + 0x0B30U)
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/* Secure Module Stop Control Register 5 */
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#define SCMSTPCR5 (CPG_BASE + 0x0B34U)
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/* Secure Module Stop Control Register 6 */
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#define SCMSTPCR6 (CPG_BASE + 0x0B38U)
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/* Secure Module Stop Control Register 7 */
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#define SCMSTPCR7 (CPG_BASE + 0x0B3CU)
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/* Secure Module Stop Control Register 8 */
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#define SCMSTPCR8 (CPG_BASE + 0x0B40U)
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/* Secure Module Stop Control Register 9 */
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#define SCMSTPCR9 (CPG_BASE + 0x0B44U)
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/* Secure Module Stop Control Register 10 */
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#define SCMSTPCR10 (CPG_BASE + 0x0B48U)
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/* Secure Module Stop Control Register 11 */
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#define SCMSTPCR11 (CPG_BASE + 0x0B4CU)
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/* CPG (SECURITY) registers */
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/* Secure Software Reset Access Enable Control Register 0 */
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#define SCSRSTECR0 (CPG_BASE + 0x0B80U)
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/* Secure Software Reset Access Enable Control Register 1 */
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#define SCSRSTECR1 (CPG_BASE + 0x0B84U)
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/* Secure Software Reset Access Enable Control Register 2 */
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#define SCSRSTECR2 (CPG_BASE + 0x0B88U)
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/* Secure Software Reset Access Enable Control Register 3 */
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#define SCSRSTECR3 (CPG_BASE + 0x0B8CU)
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/* Secure Software Reset Access Enable Control Register 4 */
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#define SCSRSTECR4 (CPG_BASE + 0x0B90U)
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/* Secure Software Reset Access Enable Control Register 5 */
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#define SCSRSTECR5 (CPG_BASE + 0x0B94U)
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/* Secure Software Reset Access Enable Control Register 6 */
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#define SCSRSTECR6 (CPG_BASE + 0x0B98U)
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/* Secure Software Reset Access Enable Control Register 7 */
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#define SCSRSTECR7 (CPG_BASE + 0x0B9CU)
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/* Secure Software Reset Access Enable Control Register 8 */
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#define SCSRSTECR8 (CPG_BASE + 0x0BA0U)
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/* Secure Software Reset Access Enable Control Register 9 */
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#define SCSRSTECR9 (CPG_BASE + 0x0BA4U)
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/* Secure Software Reset Access Enable Control Register 10 */
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#define SCSRSTECR10 (CPG_BASE + 0x0BA8U)
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/* Secure Software Reset Access Enable Control Register 11 */
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#define SCSRSTECR11 (CPG_BASE + 0x0BACU)
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/* CPG (REALTIME) registers */
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/* Realtime Module Stop Control Register 0 */
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#define RMSTPCR0 (CPG_BASE + 0x0110U)
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/* Realtime Module Stop Control Register 1 */
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#define RMSTPCR1 (CPG_BASE + 0x0114U)
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/* Realtime Module Stop Control Register 2 */
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#define RMSTPCR2 (CPG_BASE + 0x0118U)
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/* Realtime Module Stop Control Register 3 */
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#define RMSTPCR3 (CPG_BASE + 0x011CU)
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/* Realtime Module Stop Control Register 4 */
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#define RMSTPCR4 (CPG_BASE + 0x0120U)
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/* Realtime Module Stop Control Register 5 */
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#define RMSTPCR5 (CPG_BASE + 0x0124U)
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/* Realtime Module Stop Control Register 6 */
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#define RMSTPCR6 (CPG_BASE + 0x0128U)
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/* Realtime Module Stop Control Register 7 */
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#define RMSTPCR7 (CPG_BASE + 0x012CU)
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/* Realtime Module Stop Control Register 8 */
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#define RMSTPCR8 (CPG_BASE + 0x0980U)
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/* Realtime Module Stop Control Register 9 */
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#define RMSTPCR9 (CPG_BASE + 0x0984U)
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/* Realtime Module Stop Control Register 10 */
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#define RMSTPCR10 (CPG_BASE + 0x0988U)
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/* Realtime Module Stop Control Register 11 */
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#define RMSTPCR11 (CPG_BASE + 0x098CU)
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/* CPG (SYSTEM) registers */
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/* System Module Stop Control Register 0 */
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#define SMSTPCR0 (CPG_BASE + 0x0130U)
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/* System Module Stop Control Register 1 */
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#define SMSTPCR1 (CPG_BASE + 0x0134U)
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/* System Module Stop Control Register 2 */
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#define SMSTPCR2 (CPG_BASE + 0x0138U)
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/* System Module Stop Control Register 3 */
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#define SMSTPCR3 (CPG_BASE + 0x013CU)
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/* System Module Stop Control Register 4 */
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#define SMSTPCR4 (CPG_BASE + 0x0140U)
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/* System Module Stop Control Register 5 */
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#define SMSTPCR5 (CPG_BASE + 0x0144U)
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/* System Module Stop Control Register 6 */
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#define SMSTPCR6 (CPG_BASE + 0x0148U)
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/* System Module Stop Control Register 7 */
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#define SMSTPCR7 (CPG_BASE + 0x014CU)
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/* System Module Stop Control Register 8 */
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#define SMSTPCR8 (CPG_BASE + 0x0990U)
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/* System Module Stop Control Register 9 */
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#define SMSTPCR9 (CPG_BASE + 0x0994U)
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/* System Module Stop Control Register 10 */
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#define SMSTPCR10 (CPG_BASE + 0x0998U)
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/* System Module Stop Control Register 11 */
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#define SMSTPCR11 (CPG_BASE + 0x099CU)
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#endif /* CPG_REGISTERS_H */
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