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db9ee83432
The errata framework has a helper to invoke workarounds, complete with a cpu rev_var check. We can use that directly instead of the apply_cpu_pwr_dwn_errata to save on some code, as well as an extra branch. It's also more readable. Also, apply_erratum invocation in cpu files don't need to check the rev_var as that was already done by the cpu_ops dispatcher for us to end up in the file. Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e. at runtime. It doesn't achieve anything at reset, so we can label it accordingly. Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
191 lines
5.7 KiB
ArmAsm
191 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a77.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
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/* move cpu revision in again and compare against r0p0 */
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mov x0, x7
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mov x1, #CPU_REV(0, 0)
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bl cpu_rev_var_ls
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cbz x0, 1f
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x4004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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ldr x0, =0x1
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8C00040
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00040
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msr CORTEX_A77_CPUPMR_EL3, x0
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b 2f
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1:
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FF600000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x00E8E00080
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msr CORTEX_A77_CPUPOR2_EL3, x0
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ldr x0, =0x00FFE000C0
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msr CORTEX_A77_CPUPMR2_EL3, x0
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2:
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ldr x0, =0x04004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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workaround_reset_end cortex_a77, ERRATUM(1508412)
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check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
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workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
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sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
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workaround_reset_end cortex_a77, ERRATUM(1791578)
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check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
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/* Disable allocation of splintered pages in the L2 TLB */
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
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workaround_reset_end cortex_a77, ERRATUM(1800714)
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check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
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workaround_reset_end cortex_a77, ERRATUM(1925769)
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check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
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ldr x0,=0x4
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3900002
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF00083
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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ldr x0,=0x5
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3800082
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF00083
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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ldr x0,=0x6
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3800200
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF003E0
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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workaround_reset_end cortex_a77, ERRATUM(1946167)
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check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
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sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
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workaround_reset_end cortex_a77, ERRATUM(2356587)
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check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
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workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
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check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A77 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a77
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a77, CVE(2022, 23960)
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check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
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* -------------------------------------------------
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*/
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cpu_reset_func_start cortex_a77
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cpu_reset_func_end cortex_a77
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a77_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
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CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_a77_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-A77 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a77_regs, "aS"
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cortex_a77_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a77_cpu_reg_dump
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adr x6, cortex_a77_regs
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mrs x8, CORTEX_A77_CPUECTLR_EL1
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ret
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endfunc cortex_a77_cpu_reg_dump
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declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
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cortex_a77_reset_func, \
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cortex_a77_core_pwr_dwn
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