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c7e698cfde
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1, and is still open. The workaround is to disable the use of the Full Retention power mode in the core (setting WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000). SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
186 lines
4.9 KiB
ArmAsm
186 lines
4.9 KiB
ArmAsm
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x3_core_pwr_dwn
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#if ERRATA_X3_2313909
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mov x15, x30
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bl cpu_get_rev_var
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bl errata_cortex_x3_2313909_wa
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mov x30, x15
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#endif /* ERRATA_X3_2313909 */
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_X3_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_x3_core_pwr_dwn
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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func cortex_x3_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-X3 generic vectors are overridden to apply
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* errata mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_x3
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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bl cpu_get_rev_var
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#if ERRATA_X3_2615812
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bl errata_cortex_x3_2615812_wa
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#endif /* ERRATA_X3_2615812 */
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isb
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ret x19
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endfunc cortex_x3_reset_func
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/* ----------------------------------------------------------------------
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* Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
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* This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* ----------------------------------------------------------------------
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*/
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func errata_cortex_x3_2313909_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2313909
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cbz x0, 1f
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/* Set bit 36 in ACTLR2_EL1 */
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mrs x1, CORTEX_X3_CPUACTLR2_EL1
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orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
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msr CORTEX_X3_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_cortex_x3_2313909_wa
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func check_errata_2313909
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2313909
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/* ----------------------------------------------------------------------
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* Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
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* This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* ----------------------------------------------------------------------
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*/
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func errata_cortex_x3_2615812_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2615812
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cbz x0, 1f
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/* Disable retention control for WFI and WFE. */
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mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
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msr CORTEX_X3_CPUPWRCTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_x3_2615812_wa
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func check_errata_2615812
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/* Applies to r1p1 and below. */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2615812
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-X3. Must follow AAPCS.
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*/
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func cortex_x3_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_X3_2313909, cortex_x3, 2313909
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report_errata ERRATA_X3_2615812, cortex_x3, 2615812
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report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_x3_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex-X3-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x3_regs, "aS"
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cortex_x3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x3_cpu_reg_dump
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adr x6, cortex_x3_regs
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mrs x8, CORTEX_X3_CPUECTLR_EL1
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ret
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endfunc cortex_x3_cpu_reg_dump
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declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
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cortex_x3_reset_func, \
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cortex_x3_core_pwr_dwn
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