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2644103063
During the warm boot sequence: 1. The MMU is enabled with the data cache disabled. The MMU table walker is set up to access the translation tables as in cacheable memory, but its accesses are non-cacheable because SCTLR_EL3.C controls them as well. 2. The interconnect is set up and the CPU enters coherency with the rest of the system. 3. The data cache is enabled. If the support for dynamic translation tables is enabled and another CPU makes changes to a region, the changes may only be present in the data cache, not in RAM. The CPU that is booting isn't in coherency with the rest of the system, so the table walker of that CPU isn't either. This means that it may read old entries from RAM and it may have invalid TLB entries corresponding to the dynamic mappings. This is not a problem for the boot code because the mapping is 1:1 and the regions are static. However, the code that runs after the boot sequence may need to access the dynamically mapped regions. This patch invalidates all TLBs during warm boot when the dynamic translation tables support is enabled to prevent this problem. Change-Id: I80264802dc0aa1cb3edd77d0b66b91db6961af3d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
164 lines
4.9 KiB
ArmAsm
164 lines
4.9 KiB
ArmAsm
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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#include <psci.h>
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.globl psci_do_pwrdown_cache_maintenance
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.globl psci_do_pwrup_cache_maintenance
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.globl psci_power_down_wfi
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#if !ERROR_DEPRECATED
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.globl psci_entrypoint
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#endif
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/* -----------------------------------------------------------------------
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* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
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*
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* This function performs cache maintenance for the specified power
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* level. The levels of cache affected are determined by the power
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* level which is passed as the argument i.e. level 0 results
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* in a flush of the L1 cache. Both the L1 and L2 caches are flushed
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* for a higher power level.
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*
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* Additionally, this function also ensures that stack memory is correctly
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* flushed out to avoid coherency issues due to a change in its memory
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* attributes after the data cache is disabled.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrdown_cache_maintenance
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stp x29, x30, [sp,#-16]!
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stp x19, x20, [sp,#-16]!
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/* ---------------------------------------------
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* Invoke CPU-specific power down operations for
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* the appropriate level
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* ---------------------------------------------
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*/
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bl prepare_cpu_pwr_dwn
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/* ---------------------------------------------
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* Do stack maintenance by flushing the used
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* stack to the main memory and invalidating the
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* remainder.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1.
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* ---------------------------------------------
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*/
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mov x19, x0
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl flush_dcache_range
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/* ---------------------------------------------
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* Calculate and store the size of the unused
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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sub x0, x19, #PLATFORM_STACK_SIZE
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sub x1, sp, x0
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bl inv_dcache_range
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ldp x19, x20, [sp], #16
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrdown_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrup_cache_maintenance(void);
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*
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* This function performs cache maintenance after this cpu is powered up.
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* Currently, this involves managing the used stack memory before turning
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* on the data cache.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrup_cache_maintenance
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stp x29, x30, [sp,#-16]!
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* to main memory.
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* ---------------------------------------------
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*/
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dmb st
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl inv_dcache_range
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/* ---------------------------------------------
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* Enable the data cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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orr x0, x0, #SCTLR_C_BIT
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msr sctlr_el3, x0
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isb
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#if PLAT_XLAT_TABLES_DYNAMIC
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/* ---------------------------------------------
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* During warm boot the MMU is enabled with data
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* cache disabled, then the interconnect is set
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* up and finally the data cache is enabled.
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*
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* During this period, if another CPU modifies
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* the translation tables, the MMU table walker
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* may read the old entries. This is only a
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* problem for dynamic regions, the warm boot
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* code isn't affected because it is static.
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*
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* Invalidate all TLB entries loaded while the
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* CPU wasn't coherent with the rest of the
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* system.
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* ---------------------------------------------
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*/
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tlbi alle3
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dsb ish
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isb
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#endif
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrup_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_power_down_wfi(void);
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* This function is called to indicate to the power controller that it
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* is safe to power down this cpu. It should not exit the wfi and will
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* be released from reset upon power up.
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* -----------------------------------------------------------------------
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*/
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func psci_power_down_wfi
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dsb sy // ensure write buffer empty
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wfi
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no_ret plat_panic_handler
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endfunc psci_power_down_wfi
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/* -----------------------------------------------------------------------
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* void psci_entrypoint(void);
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* The deprecated entry point for PSCI on warm boot for AArch64.
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* -----------------------------------------------------------------------
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*/
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func_deprecated psci_entrypoint
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b bl31_warm_entrypoint
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endfunc_deprecated psci_entrypoint
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