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Currently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source directory. The "sgi" prefix originated from the System Guidance for Infrastructure (SGI) and was initially associated with the SGI-575 platform. However, subsequent platforms released were under the Neoverse Reference Design product name. To align with the Neoverse Reference Design nomenclature, rename the common source directory from "css/sgi" to "css/neoverse_rd" and update all file prefixes from "sgi" to "nrd." Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I3dcbb31b9ab202e82caf25218ba33c520dcea4e4
112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
/*
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* Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl31/interrupt_mgmt.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include <services/sdei.h>
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#include <services/spm_mm_svc.h>
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#include <platform_def.h>
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#include <nrd_ras.h>
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/* Base Element RAM Error Record offsets. */
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#define ERRSTATUS U(0)
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#define ERRCODE U(8)
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#define ERRADDR U(12)
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/*
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* Base Element RAM error information data structure communicated as part of MM
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* Communication data payload.
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*/
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typedef struct sgi_sram_err_info {
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uint32_t err_status;
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uint32_t err_code;
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uint32_t err_addr;
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} sgi_sram_err_info_t;
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/*
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* MM Communicate message header GUID to indicate the payload is intended for
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* base element RAM MM driver.
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*/
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struct efi_guid sram_ecc_event_guid = {
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0x7312db4f, 0xd0c4, 0x4fb5,
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{ 0x81, 0x2c, 0xb7, 0x4b, 0xc6, 0xc4, 0xa9, 0x38 }
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};
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/* Base element RAM RAS error interrupt handler */
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int sgi_ras_sram_intr_handler(const struct err_record_info *err_rec,
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int probe_data,
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const struct err_handler_data *const data)
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{
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struct sgi_ras_ev_map *ras_map;
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mm_communicate_header_t *header;
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sgi_sram_err_info_t sram_info;
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uintptr_t base_addr;
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uint32_t clear_status, intr;
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int ret;
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cm_el1_sysregs_context_save(NON_SECURE);
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intr = data->interrupt;
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INFO("SGI: Base element RAM interrupt [%d] handler\n", intr);
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/* Determine error record base address to read. */
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base_addr = 0;
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if (intr == NS_RAM_ECC_CE_INT || intr == NS_RAM_ECC_UE_INT) {
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base_addr = SOC_NS_RAM_ERR_REC_BASE;
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}
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sram_info.err_status = mmio_read_32(base_addr + ERRSTATUS);
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sram_info.err_code = mmio_read_32(base_addr + ERRCODE);
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sram_info.err_addr = mmio_read_32(base_addr + ERRADDR);
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/* Clear the interrupt. */
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clear_status = mmio_read_32(base_addr + ERRSTATUS);
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mmio_write_32((base_addr + ERRSTATUS), clear_status);
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/*
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* Prepare the MM Communication buffer to pass the base element RAM
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* error information to Secure Partition.
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*/
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header = (void *)PLAT_SPM_BUF_BASE;
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memset(header, 0, sizeof(*header));
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memcpy(&header->data, &sram_info, sizeof(sram_info));
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header->message_len = sizeof(sram_info);
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memcpy(&header->header_guid, (void *)&sram_ecc_event_guid,
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sizeof(struct efi_guid));
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spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
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plat_my_core_pos());
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plat_ic_end_of_interrupt(intr);
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/*
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* Find if this is a RAS interrupt. There must be an event against
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* this interrupt
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*/
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ras_map = sgi_find_ras_event_map_by_intr(intr);
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if (ras_map == NULL) {
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ERROR("SGI: RAS error info for interrupt id: %d not found\n",
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intr);
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return -1;
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}
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/* Dispatch the event to the SDEI client */
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ret = sdei_dispatch_event(ras_map->sdei_ev_num);
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if (ret != 0) {
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/*
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* sdei_dispatch_event() may return failing result in some
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* cases, for example kernel may not have registered a handler
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* or RAS event may happen early during boot. We restore the NS
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* context when sdei_dispatch_event() returns failing result.
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*/
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ERROR("SDEI dispatch failed: %d", ret);
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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}
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return ret;
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}
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