mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
c669f65359
Currently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source directory. The "sgi" prefix originated from the System Guidance for Infrastructure (SGI) and was initially associated with the SGI-575 platform. However, subsequent platforms released were under the Neoverse Reference Design product name. To align with the Neoverse Reference Design nomenclature, rename the common source directory from "css/sgi" to "css/neoverse_rd" and update all file prefixes from "sgi" to "nrd." Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I3dcbb31b9ab202e82caf25218ba33c520dcea4e4
79 lines
2.8 KiB
C
79 lines
2.8 KiB
C
/*
|
|
* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <common/debug.h>
|
|
#include <plat/arm/common/plat_arm.h>
|
|
#include <plat/arm/css/common/css_pm.h>
|
|
|
|
#include <nrd_variant.h>
|
|
|
|
/******************************************************************************
|
|
* The power domain tree descriptor.
|
|
******************************************************************************/
|
|
const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
|
|
((PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT)),
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
#if (CSS_SGI_CHIP_COUNT > 1)
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
#endif
|
|
#if (CSS_SGI_CHIP_COUNT > 2)
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
#endif
|
|
#if (CSS_SGI_CHIP_COUNT > 3)
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
|
CSS_SGI_MAX_CPUS_PER_CLUSTER
|
|
#endif
|
|
};
|
|
|
|
/*******************************************************************************
|
|
* This function returns the topology tree information.
|
|
******************************************************************************/
|
|
const unsigned char *plat_get_power_domain_tree_desc(void)
|
|
{
|
|
if (plat_arm_sgi_get_multi_chip_mode() == 1)
|
|
return rd_v1_mc_pd_tree_desc_multi_chip;
|
|
panic();
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* The array mapping platform core position (implemented by plat_my_core_pos())
|
|
* to the SCMI power domain ID implemented by SCP.
|
|
******************************************************************************/
|
|
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
|
|
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
|
|
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
|
|
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
|
|
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
|
|
#if (CSS_SGI_CHIP_COUNT > 1)
|
|
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
|
|
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
|
|
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
|
|
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
|
|
#endif
|
|
#if (CSS_SGI_CHIP_COUNT > 2)
|
|
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
|
|
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
|
|
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
|
|
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
|
|
#endif
|
|
#if (CSS_SGI_CHIP_COUNT > 3)
|
|
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
|
|
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
|
|
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
|
|
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
|
|
#endif
|
|
};
|