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c669f65359
Currently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source directory. The "sgi" prefix originated from the System Guidance for Infrastructure (SGI) and was initially associated with the SGI-575 platform. However, subsequent platforms released were under the Neoverse Reference Design product name. To align with the Neoverse Reference Design nomenclature, rename the common source directory from "css/sgi" to "css/neoverse_rd" and update all file prefixes from "sgi" to "nrd." Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I3dcbb31b9ab202e82caf25218ba33c520dcea4e4
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/gic600_multichip.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <nrd_plat.h>
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#include <nrd_soc_platform_def.h>
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#if defined(IMAGE_BL31)
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static const mmap_region_t rdn1edge_dynamic_mmap[] = {
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ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
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CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
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SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
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};
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static struct gic600_multichip_data rdn1e1_multichip_data __init = {
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.rt_owner_base = PLAT_ARM_GICD_BASE,
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.rt_owner = 0,
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.chip_count = CSS_SGI_CHIP_COUNT,
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.chip_addrs = {
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PLAT_ARM_GICD_BASE >> 16,
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(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
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},
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.spi_ids = {
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{PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START,
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RDN1E1_CHIP0_SPI_END},
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{0, 0, 0}
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}
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};
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static uintptr_t rdn1e1_multichip_gicr_frames[] = {
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PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
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PLAT_ARM_GICR_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
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UL(0) /* Zero Termination */
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};
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#endif /* IMAGE_BL31 */
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unsigned int plat_arm_sgi_get_platform_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
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& SID_SYSTEM_ID_PART_NUM_MASK;
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}
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unsigned int plat_arm_sgi_get_config_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
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}
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unsigned int plat_arm_sgi_get_multi_chip_mode(void)
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{
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return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
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SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
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}
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/*
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* IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
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* because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
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* for other stages.
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*/
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#if defined(IMAGE_BL31)
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void bl31_platform_setup(void)
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{
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unsigned int i;
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int ret;
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if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) {
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ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
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CSS_SGI_CHIP_COUNT);
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panic();
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} else if (plat_arm_sgi_get_multi_chip_mode() == 1 &&
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CSS_SGI_CHIP_COUNT > 1) {
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INFO("Enabling support for multi-chip in RD-N1-Edge\n");
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for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
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ret = mmap_add_dynamic_region(
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rdn1edge_dynamic_mmap[i].base_pa,
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rdn1edge_dynamic_mmap[i].base_va,
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rdn1edge_dynamic_mmap[i].size,
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rdn1edge_dynamic_mmap[i].attr
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);
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if (ret != 0) {
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ERROR("Failed to add dynamic mmap entry\n");
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panic();
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}
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}
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plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
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gic600_multichip_init(&rdn1e1_multichip_data);
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}
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sgi_bl31_common_platform_setup();
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}
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#endif /* IMAGE_BL31 */
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