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MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
34 lines
1.2 KiB
ReStructuredText
34 lines
1.2 KiB
ReStructuredText
Activity Monitors
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=================
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FEAT_AMUv1 of the Armv8-A architecture introduces the Activity Monitors
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extension. This extension describes the architecture for the Activity Monitor
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Unit (|AMU|), an optional non-invasive component for monitoring core events
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through a set of 64-bit counters.
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When the ``ENABLE_AMU=1`` build option is provided, Trusted Firmware-A sets up
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the |AMU| prior to its exit from EL3, and will save and restore architected
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|AMU| counters as necessary upon suspend and resume.
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.. _Activity Monitor Auxiliary Counters:
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Auxiliary counters
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------------------
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FEAT_AMUv1 describes a set of implementation-defined auxiliary counters (also
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known as group 1 counters), controlled by the ``ENABLE_AMU_AUXILIARY_COUNTERS``
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build option.
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As a security precaution, Trusted Firmware-A does not enable these by default.
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Instead, platforms may configure their auxiliary counters through one of two
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possible mechanisms:
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- |FCONF|, controlled by the ``ENABLE_AMU_FCONF`` build option.
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- A platform implementation of the ``plat_amu_topology`` function (the default).
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See :ref:`Activity Monitor Unit (AMU) Bindings` for documentation on the |FCONF|
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device tree bindings.
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--------------
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*Copyright (c) 2021, Arm Limited. All rights reserved.*
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