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a0674ab081
* Currently, EL1 context is included in cpu_context_t by default for all the build configurations. As part of the cpu context structure, we hold a copy of EL1, EL2 system registers, per world per PE. This context structure is enormous and will continue to grow bigger with the addition of new features incorporating new registers. * Ideally, EL3 should save and restore the system registers at its next lower exception level, which is EL2 in majority of the configurations. * This patch aims at optimising the memory allocation in cases, when the members from the context structure are unused. So el1 system register context must be omitted when lower EL is always x-EL2. * "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set, when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1. It indicates, the system registers at EL2 are context switched for the respective build configuration. Here, there is no need to save and restore EL1 system registers, while x-EL2 is enabled. Henceforth, this patch addresses this issue, by taking out the EL1 context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is enabled, there by saving memory. Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_MGMT_H
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#define CONTEXT_MGMT_H
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#include <assert.h>
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#include <context.h>
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#include <stdint.h>
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#include <arch.h>
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct entry_point_info;
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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void cm_init(void);
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void *cm_get_context_by_index(unsigned int cpu_idx,
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unsigned int security_state);
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void cm_set_context_by_index(unsigned int cpu_idx,
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void *context,
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unsigned int security_state);
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void *cm_get_context(uint32_t security_state);
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void cm_set_context(void *context, uint32_t security_state);
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void cm_init_my_context(const struct entry_point_info *ep);
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void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
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void cm_prepare_el3_exit(uint32_t security_state);
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void cm_prepare_el3_exit_ns(void);
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#if !IMAGE_BL1
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void cm_init_context_by_index(unsigned int cpu_idx,
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const struct entry_point_info *ep);
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#endif /* !IMAGE_BL1 */
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#ifdef __aarch64__
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#if IMAGE_BL31
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void cm_manage_extensions_el3(void);
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void manage_extensions_nonsecure_per_world(void);
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void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
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void cm_handle_asymmetric_features(void);
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#endif
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#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
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void cm_el2_sysregs_context_save(uint32_t security_state);
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void cm_el2_sysregs_context_restore(uint32_t security_state);
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#else
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void cm_el1_sysregs_context_save(uint32_t security_state);
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void cm_el1_sysregs_context_restore(uint32_t security_state);
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#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
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void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
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void cm_set_elr_spsr_el3(uint32_t security_state,
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uintptr_t entrypoint, uint32_t spsr);
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void cm_write_scr_el3_bit(uint32_t security_state,
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uint32_t bit_pos,
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uint32_t value);
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void cm_set_next_eret_context(uint32_t security_state);
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u_register_t cm_get_scr_el3(uint32_t security_state);
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/* Inline definitions */
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/*******************************************************************************
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* This function is used to program the context that's used for exception
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* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
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* the required security state
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******************************************************************************/
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static inline void cm_set_next_context(void *context)
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{
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#if ENABLE_ASSERTIONS
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uint64_t sp_mode;
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/*
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* Check that this function is called with SP_EL0 as the stack
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* pointer
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*/
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__asm__ volatile("mrs %0, SPSel\n"
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: "=r" (sp_mode));
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assert(sp_mode == MODE_SP_EL0);
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#endif /* ENABLE_ASSERTIONS */
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__asm__ volatile("msr spsel, #1\n"
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"mov sp, %0\n"
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"msr spsel, #0\n"
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: : "r" (context));
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}
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#else
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void *cm_get_next_context(void);
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void cm_set_next_context(void *context);
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static inline void cm_manage_extensions_el3(void) {}
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static inline void manage_extensions_nonsecure_per_world(void) {}
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static inline void cm_handle_asymmetric_features(void) {}
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#endif /* __aarch64__ */
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#endif /* CONTEXT_MGMT_H */
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