mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
8cd37d7ba1
BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <xlat_tables_v2.h>
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#define SQ_REG_REGION_BASE 0x20000000ULL
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#define SQ_REG_REGION_SIZE 0x60000000ULL
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void sq_mmap_setup(uintptr_t total_base, size_t total_size,
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const struct mmap_region *mmap)
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{
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VERBOSE("Trusted RAM seen by this BL image: %p - %p\n",
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(void *)total_base, (void *)(total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE);
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/* remap the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *)BL_CODE_BASE, (void *)BL_CODE_END);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE,
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MT_NON_CACHEABLE | MT_RO | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END);
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mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
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round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE,
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(MT_NON_CACHEABLE | MT_RO | MT_EXECUTE_NEVER |
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MT_SECURE));
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/* remap the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END);
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/* register region */
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mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE,
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SQ_REG_REGION_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/* additional regions if needed */
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if (mmap)
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mmap_add(mmap);
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init_xlat_tables();
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}
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