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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
316 lines
11 KiB
ArmAsm
316 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EL3_COMMON_MACROS_S
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#define EL3_COMMON_MACROS_S
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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/*
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* Helper macro to initialise EL3 registers we care about.
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*/
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.macro el3_arch_init_common
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/* ---------------------------------------------------------------------
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* SCTLR has already been initialised - read current value before
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* modifying.
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*
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* SCTLR.I: Enable the instruction cache.
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*
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* SCTLR.A: Enable Alignment fault checking. All instructions that load
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* or store one or more registers have an alignment check that the
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* address being accessed is aligned to the size of the data element(s)
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* being accessed.
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* ---------------------------------------------------------------------
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*/
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ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
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ldcopr r0, SCTLR
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orr r0, r0, r1
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stcopr r0, SCTLR
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isb
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/* ---------------------------------------------------------------------
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* Initialise SCR, setting all fields rather than relying on the hw.
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*
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* SCR.SIF: Enabled so that Secure state instruction fetches from
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* Non-secure memory are not permitted.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
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stcopr r0, SCR
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/* -----------------------------------------------------
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* Enable the Asynchronous data abort now that the
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* exception vectors have been setup.
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* -----------------------------------------------------
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*/
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cpsie a
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isb
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/* ---------------------------------------------------------------------
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* Initialise NSACR, setting all the fields, except for the
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* IMPLEMENTATION DEFINED field, rather than relying on the hw. Some
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* fields are architecturally UNKNOWN on reset.
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*
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* NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The
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* cp11 field is ignored, but is set to same value as cp10. The cp10
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* field is set to allow access to Advanced SIMD and floating point
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* features from both Security states.
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* ---------------------------------------------------------------------
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*/
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ldcopr r0, NSACR
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and r0, r0, #NSACR_IMP_DEF_MASK
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orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
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stcopr r0, NSACR
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isb
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/* ---------------------------------------------------------------------
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* Initialise CPACR, setting all fields rather than relying on hw. Some
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* fields are architecturally UNKNOWN on reset.
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*
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* CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses
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* to trace registers. Set to zero to allow access.
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*
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* CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The
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* cp11 field is ignored, but is set to same value as cp10. The cp10
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* field is set to allow full access from PL0 and PL1 to floating-point
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* and Advanced SIMD features.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT))
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stcopr r0, CPACR
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isb
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/* ---------------------------------------------------------------------
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* Initialise FPEXC, setting all fields rather than relying on hw. Some
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* fields are architecturally UNKNOWN on reset and are set to zero
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* except for field(s) listed below.
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*
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* FPEXC.EN: Enable access to Advanced SIMD and floating point features
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* from all exception levels.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
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vmsr FPEXC, r0
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isb
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#if (ARM_ARCH_MAJOR > 7)
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/* ---------------------------------------------------------------------
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* Initialise SDCR, setting all the fields rather than relying on hw.
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*
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* SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from
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* Secure EL1 are disabled.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE))
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stcopr r0, SDCR
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#endif
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.endm
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/* -----------------------------------------------------------------------------
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* This is the super set of actions that need to be performed during a cold boot
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* or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
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*
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* This macro will always perform reset handling, architectural initialisations
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* and stack setup. The rest of the actions are optional because they might not
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* be needed, depending on the context in which this macro is called. This is
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* why this macro is parameterised ; each parameter allows to enable/disable
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* some actions.
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*
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* _init_sctlr:
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* Whether the macro needs to initialise the SCTLR register including
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* configuring the endianness of data accesses.
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*
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* _warm_boot_mailbox:
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* Whether the macro needs to detect the type of boot (cold/warm). The
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* detection is based on the platform entrypoint address : if it is zero
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* then it is a cold boot, otherwise it is a warm boot. In the latter case,
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* this macro jumps on the platform entrypoint address.
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*
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* _secondary_cold_boot:
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* Whether the macro needs to identify the CPU that is calling it: primary
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* CPU or secondary CPU. The primary CPU will be allowed to carry on with
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* the platform initialisations, while the secondaries will be put in a
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* platform-specific state in the meantime.
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*
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* If the caller knows this macro will only be called by the primary CPU
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* then this parameter can be defined to 0 to skip this step.
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*
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* _init_memory:
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* Whether the macro needs to initialise the memory.
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*
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* _init_c_runtime:
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* Whether the macro needs to initialise the C runtime environment.
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*
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* _exception_vectors:
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* Address of the exception vectors to program in the VBAR_EL3 register.
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* -----------------------------------------------------------------------------
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*/
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.macro el3_entrypoint_common \
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_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
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_init_memory, _init_c_runtime, _exception_vectors
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/* Make sure we are in Secure Mode */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCR
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tst r0, #SCR_NS_BIT
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ASM_ASSERT(eq)
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#endif
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.if \_init_sctlr
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/* -------------------------------------------------------------
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* This is the initialisation of SCTLR and so must ensure that
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* all fields are explicitly set rather than relying on hw. Some
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* fields reset to an IMPLEMENTATION DEFINED value.
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*
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* SCTLR.TE: Set to zero so that exceptions to an Exception
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* Level executing at PL1 are taken to A32 state.
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*
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* SCTLR.EE: Set the CPU endianness before doing anything that
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* might involve memory reads or writes. Set to zero to select
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* Little Endian.
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*
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* SCTLR.V: Set to zero to select the normal exception vectors
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* with base address held in VBAR.
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* -------------------------------------------------------------
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*/
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ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | SCTLR_V_BIT))
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stcopr r0, SCTLR
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isb
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.endif /* _init_sctlr */
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/* Switch to monitor mode */
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cps #MODE32_mon
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isb
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.if \_warm_boot_mailbox
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/* -------------------------------------------------------------
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* This code will be executed for both warm and cold resets.
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* Now is the time to distinguish between the two.
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* Query the platform entrypoint address and if it is not zero
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* then it means it is a warm boot so jump to this address.
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* -------------------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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cmp r0, #0
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bxne r0
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.endif /* _warm_boot_mailbox */
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/* ---------------------------------------------------------------------
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* Set the exception vectors (VBAR/MVBAR).
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* ---------------------------------------------------------------------
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*/
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ldr r0, =\_exception_vectors
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stcopr r0, VBAR
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stcopr r0, MVBAR
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isb
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/* ---------------------------------------------------------------------
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* It is a cold boot.
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* Perform any processor specific actions upon reset e.g. cache, TLB
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* invalidations etc.
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* ---------------------------------------------------------------------
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*/
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bl reset_handler
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el3_arch_init_common
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* Check if this is a primary or secondary CPU cold boot.
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* The primary CPU will set up the platform while the
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* secondaries are placed in a platform-specific state until the
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* primary CPU performs the necessary actions to bring them out
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* of that state and allows entry into the OS.
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* -------------------------------------------------------------
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*/
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bl plat_is_my_cpu_primary
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cmp r0, #0
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bne do_primary_cold_boot
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/* This is a cold boot on a secondary CPU */
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bl plat_secondary_cold_boot_setup
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/* plat_secondary_cold_boot_setup() is not supposed to return */
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no_ret plat_panic_handler
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do_primary_cold_boot:
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.endif /* _secondary_cold_boot */
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/* ---------------------------------------------------------------------
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* Initialize memory now. Secondary CPU initialization won't get to this
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* point.
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* ---------------------------------------------------------------------
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*/
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.if \_init_memory
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bl platform_mem_init
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.endif /* _init_memory */
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/* ---------------------------------------------------------------------
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* Init C runtime environment:
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* - Zero-initialise the NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section (if any).
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* - Relocate the data section from ROM to RAM, if required.
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* ---------------------------------------------------------------------
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*/
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.if \_init_c_runtime
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#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
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/* -----------------------------------------------------------------
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* Invalidate the RW memory used by the image. This
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* includes the data and NOBITS sections. This is done to
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* safeguard against possible corruption of this memory by
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* dirty cache lines in a system cache as a result of use by
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* an earlier boot loader stage.
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* -----------------------------------------------------------------
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*/
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ldr r0, =__RW_START__
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ldr r1, =__RW_END__
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sub r1, r1, r0
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bl inv_dcache_range
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#endif
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_SIZE__
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bl zeromem
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#if USE_COHERENT_MEM
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ldr r0, =__COHERENT_RAM_START__
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ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem
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#endif
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#ifdef IMAGE_BL1
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/* -----------------------------------------------------
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* Copy data from ROM to RAM.
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* -----------------------------------------------------
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*/
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ldr r0, =__DATA_RAM_START__
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ldr r1, =__DATA_ROM_START__
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ldr r2, =__DATA_SIZE__
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bl memcpy4
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#endif
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.endif /* _init_c_runtime */
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/* ---------------------------------------------------------------------
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* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
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* the MMU is enabled. There is no risk of reading stale stack memory
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* after enabling the MMU as only the primary CPU is running at the
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* moment.
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* ---------------------------------------------------------------------
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*/
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bl plat_set_my_stack
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#if STACK_PROTECTOR_ENABLED
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.if \_init_c_runtime
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bl update_stack_protector_canary
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.endif /* _init_c_runtime */
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#endif
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.endm
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#endif /* EL3_COMMON_MACROS_S */
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