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https://github.com/ARM-software/arm-trusted-firmware.git
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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
474 lines
20 KiB
C
474 lines
20 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file emmc_std.h
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* @brief eMMC boot is expecting this header file
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*
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*/
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#ifndef EMMC_STD_H
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#define EMMC_STD_H
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#include "emmc_hal.h"
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/* ************************ HEADER (INCLUDE) SECTION *********************** */
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/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
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#ifndef FALSE
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#define FALSE 0U
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#endif
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#ifndef TRUE
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#define TRUE 1U
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#endif
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/** @brief 64bit registers
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**/
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#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
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#define GETR_64(r) (*(volatile uint64_t *)(r))
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/** @brief 32bit registers
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**/
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#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
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#define GETR_32(r) (*(volatile uint32_t *)(r))
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/** @brief 16bit registers
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*/
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#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
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#define GETR_16(r) (*(volatile uint16_t *)(r))
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/** @brief 8bit registers
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*/
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#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
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#define GETR_8(r) (*(volatile uint8_t *)(r))
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/** @brief CSD register Macros
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*/
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#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
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#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
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#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
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#define EMMC_CID_OID() (EMMC_GET_CID(111, 104))
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#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88))
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#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56))
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#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48))
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#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16))
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#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
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#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
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/** @brief CSD register Macros
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*/
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#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
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#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
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#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
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#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
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#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
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#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
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#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
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#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
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#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
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#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
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#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
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#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
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#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
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#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
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#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
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#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
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#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
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#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
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#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
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#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
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#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
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#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
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#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
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#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
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#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
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#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
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#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
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#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
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#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
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#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
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#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
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#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
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#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
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#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
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/** @brief for sector access
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*/
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#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
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#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
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#define EMMC_SECTOR_SIZE 512
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#define EMMC_BLOCK_LENGTH 512
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#define EMMC_BLOCK_LENGTH_DW 128
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#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
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/** @brief eMMC specification clock
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*/
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#define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */
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#define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */
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#define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */
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#define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */
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#define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */
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/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
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*/
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typedef enum {
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EMMC_ERR = 0, /**< unknown error */
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EMMC_SUCCESS, /**< OK */
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EMMC_ERR_FROM_DMAC, /**< DMAC allocation error */
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EMMC_ERR_FROM_DMAC_TRANSFER, /**< DMAC transfer error */
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EMMC_ERR_CARD_STATUS_BIT, /**< card status error. Non-masked error bit was set in the card status */
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EMMC_ERR_CMD_TIMEOUT, /**< command timeout error */
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EMMC_ERR_DATA_TIMEOUT, /**< data timeout error */
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EMMC_ERR_CMD_CRC, /**< command CRC error */
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EMMC_ERR_DATA_CRC, /**< data CRC error */
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EMMC_ERR_PARAM, /**< parameter error */
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EMMC_ERR_RESPONSE, /**< response error */
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EMMC_ERR_RESPONSE_BUSY, /**< response busy error */
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EMMC_ERR_TRANSFER, /**< data transfer error */
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EMMC_ERR_READ_SECTOR, /**< read sector error */
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EMMC_ERR_WRITE_SECTOR, /**< write sector error */
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EMMC_ERR_STATE, /**< state error */
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EMMC_ERR_TIMEOUT, /**< timeout error */
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EMMC_ERR_ILLEGAL_CARD, /**< illegal card */
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EMMC_ERR_CARD_BUSY, /**< Busy state */
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EMMC_ERR_CARD_STATE, /**< card state error */
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EMMC_ERR_SET_TRACE, /**< trace information error */
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EMMC_ERR_FROM_TIMER, /**< Timer error */
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EMMC_ERR_FORCE_TERMINATE, /**< Force terminate */
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EMMC_ERR_CARD_POWER, /**< card power fail */
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EMMC_ERR_ERASE_SECTOR, /**< erase sector error */
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EMMC_ERR_INFO2 /**< exec cmd error info2 */
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} EMMC_ERROR_CODE;
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/** @brief Function number */
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#define EMMC_FUNCNO_NONE 0U
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#define EMMC_FUNCNO_DRIVER_INIT 1U
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#define EMMC_FUNCNO_CARD_POWER_ON 2U
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#define EMMC_FUNCNO_MOUNT 3U
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#define EMMC_FUNCNO_CARD_INIT 4U
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#define EMMC_FUNCNO_HIGH_SPEED 5U
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#define EMMC_FUNCNO_BUS_WIDTH 6U
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#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
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#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
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#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
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#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
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#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
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#define EMMC_FUNCNO_SET_CLOCK 12U
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#define EMMC_FUNCNO_EXEC_CMD 13U
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#define EMMC_FUNCNO_READ_SECTOR 14U
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#define EMMC_FUNCNO_WRITE_SECTOR 15U
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#define EMMC_FUNCNO_ERASE_SECTOR 16U
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#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
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/** @brief Response
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*/
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/** R1 */
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#define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */
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#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
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#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
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#define EMMC_R1_READY 0x00000100U /* bit8 */
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#define EMMC_R1_STATE_SHIFT 9
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/** R4 */
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#define EMMC_R4_RCA_MASK 0xFFFF0000UL
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#define EMMC_R4_STATUS 0x00008000UL
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/** CSD */
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#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
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#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
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#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
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#define EMMC_TRANSPEED_MULT_SHIFT 3
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/** OCR */
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#define EMMC_HOST_OCR_VALUE 0x40FF8080
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#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
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#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
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#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
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#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
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/** EXT_CSD */
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#define EMMC_EXT_CSD_S_CMD_SET 504
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#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
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#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
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#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
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#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
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#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
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#define EMMC_EXT_CSD_TRIM_MULT 232
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#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
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#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
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#define EMMC_EXT_CSD_BOOT_INFO 228
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#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
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#define EMMC_EXT_CSD_ACC_SIZE 225
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#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
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#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
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#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
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#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
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#define EMMC_EXT_CSD_S_C_VCC 220
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#define EMMC_EXT_CSD_S_C_VCCQ 219
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#define EMMC_EXT_CSD_S_A_TIMEOUT 217
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#define EMMC_EXT_CSD_SEC_COUNT 215
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#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
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#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
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#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
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#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
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#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
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#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
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#define EMMC_EXT_CSD_PWR_CL_26_360 203
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#define EMMC_EXT_CSD_PWR_CL_52_360 202
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#define EMMC_EXT_CSD_PWR_CL_26_195 201
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#define EMMC_EXT_CSD_PWR_CL_52_195 200
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#define EMMC_EXT_CSD_CARD_TYPE 196
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#define EMMC_EXT_CSD_CSD_STRUCTURE 194
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#define EMMC_EXT_CSD_EXT_CSD_REV 192
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#define EMMC_EXT_CSD_CMD_SET 191
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#define EMMC_EXT_CSD_CMD_SET_REV 189
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#define EMMC_EXT_CSD_POWER_CLASS 187
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#define EMMC_EXT_CSD_HS_TIMING 185
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#define EMMC_EXT_CSD_BUS_WIDTH 183
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#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
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#define EMMC_EXT_CSD_PARTITION_CONFIG 179
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#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
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#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
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#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
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#define EMMC_EXT_CSD_BOOT_WP 173
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#define EMMC_EXT_CSD_USER_WP 171
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#define EMMC_EXT_CSD_FW_CONFIG 169
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#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
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#define EMMC_EXT_CSD_RST_n_FUNCTION 162
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#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
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#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
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#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
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#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
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#define EMMC_EXT_CSD_GP_SIZE_MULT 154
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#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
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#define EMMC_EXT_CSD_ENH_START_ADDR 139
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#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
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#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
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#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
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#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
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#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
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#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
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/** SWITCH (CMD6) argument */
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#define EXTCSD_ACCESS_BYTE (BIT25|BIT24)
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#define EXTCSD_SET_BITS BIT24
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#define HS_TIMING_ADD (185<<16) /* H'b9 */
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#define HS_TIMING_1 (1<<8)
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#define HS_TIMING_HS200 (2<<8)
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#define HS_TIMING_HS400 (3<<8)
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#define BUS_WIDTH_ADD (183<<16) /* H'b7 */
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#define BUS_WIDTH_1 (0<<8)
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#define BUS_WIDTH_4 (1<<8)
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#define BUS_WIDTH_8 (2<<8)
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#define BUS_WIDTH_4DDR (5<<8)
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#define BUS_WIDTH_8DDR (6<<8)
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#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
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#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */
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#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
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#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */
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#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */
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#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */
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#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */
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#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */
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#define TIMING_HIGH_SPEED 1UL
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#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
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#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
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/** Bus width */
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#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
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#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
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#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
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/** for st_mmc_base */
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#define EMMC_MAX_RESPONSE_LENGTH 17
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#define EMMC_MAX_CID_LENGTH 16
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#define EMMC_MAX_CSD_LENGTH 16
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#define EMMC_MAX_EXT_CSD_LENGTH 512U
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#define EMMC_RES_REG_ALIGNED 4U
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#define EMMC_BUF_REG_ALIGNED 8U
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/** @brief for TAAC mask
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*/
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#define TAAC_TIME_UNIT_MASK (0x07)
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#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
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/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
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/** @brief Partition id
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*/
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typedef enum {
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PARTITION_ID_USER = 0x0, /**< User Area */
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PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
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PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
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PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
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PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
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PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
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PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
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PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
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PARTITION_ID_MASK = 0x7 /**< [2:0] */
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} EMMC_PARTITION_ID;
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/** @brief card state in R1 response [12:9]
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*/
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typedef enum {
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EMMC_R1_STATE_IDLE = 0,
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EMMC_R1_STATE_READY,
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EMMC_R1_STATE_IDENT,
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EMMC_R1_STATE_STBY,
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EMMC_R1_STATE_TRAN,
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EMMC_R1_STATE_DATA,
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EMMC_R1_STATE_RCV,
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EMMC_R1_STATE_PRG,
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EMMC_R1_STATE_DIS,
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EMMC_R1_STATE_BTST,
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EMMC_R1_STATE_SLEP
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} EMMC_R1_STATE;
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typedef enum {
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ESTATE_BEGIN = 0,
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ESTATE_ISSUE_CMD,
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ESTATE_NON_RESP_CMD,
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ESTATE_RCV_RESP,
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ESTATE_RCV_RESPONSE_BUSY,
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ESTATE_CHECK_RESPONSE_COMPLETE,
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ESTATE_DATA_TRANSFER,
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ESTATE_DATA_TRANSFER_COMPLETE,
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ESTATE_ACCESS_END,
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ESTATE_TRANSFER_ERROR,
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ESTATE_ERROR,
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ESTATE_END
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} EMMC_INT_STATE;
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/** @brief eMMC boot driver error information
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*/
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typedef struct {
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uint16_t num; /**< error no */
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uint16_t code; /**< error code */
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volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
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volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
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volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
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volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
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volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
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volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
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} st_error_info;
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/** @brief Command information
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*/
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typedef struct {
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HAL_MEMCARD_COMMAND cmd; /**< Command information */
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uint32_t arg; /**< argument */
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HAL_MEMCARD_OPERATION dir; /**< direction */
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uint32_t hw; /**< H/W dependence. SD_CMD register value. */
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} st_command_info;
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/** @brief MMC driver base
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*/
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typedef struct {
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st_error_info error_info; /**< error information */
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st_command_info cmd_info; /**< command information */
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/* for data transfer */
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uint32_t *buff_address_virtual; /**< Dest or Src buff */
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uint32_t *buff_address_physical; /**< Dest or Src buff */
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HAL_MEMCARD_DATA_WIDTH bus_width;
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/**< bus width */
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uint32_t trans_size; /**< transfer size for this command */
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uint32_t remain_size; /**< remain size for this command */
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uint32_t response_length; /**< response length for this command */
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uint32_t sector_size; /**< sector_size */
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|
|
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/* clock */
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uint32_t base_clock; /**< MMC host controller clock */
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uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
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uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
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uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
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|
|
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/* state flag */
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HAL_MEMCARD_PRESENCE_STATUS card_present;
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|
/**< presence status of the memory card */
|
|
uint32_t card_power_enable; /**< True : Power ON */
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|
uint32_t clock_enable; /**< True : Clock ON */
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|
uint32_t initialize; /**< True : initialize complete. */
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|
uint32_t access_mode; /**< True : sector access, FALSE : byte access */
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|
uint32_t mount; /**< True : mount complete. */
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|
uint32_t selected; /**< True : selected card. */
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|
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
|
|
/**< 0: DMA, 1:PIO */
|
|
uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */
|
|
EMMC_R1_STATE current_state; /**< card state */
|
|
volatile uint32_t during_cmd_processing; /**< True : during command processing */
|
|
volatile uint32_t during_transfer; /**< True : during transfer */
|
|
volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
|
|
volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
|
|
volatile uint32_t force_terminate; /**< force terminate flag */
|
|
volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
|
|
volatile uint32_t get_partition_access_flag;
|
|
/**< True : get partition access processing */
|
|
|
|
EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */
|
|
EMMC_PARTITION_ID partition_access; /**< Current access partition */
|
|
|
|
/* timeout */
|
|
uint32_t hs_timing; /**< high speed */
|
|
|
|
/* timeout */
|
|
uint32_t data_timeout; /**< read and write data timeout.*/
|
|
|
|
/* retry */
|
|
uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */
|
|
|
|
/* interrupt */
|
|
volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
|
|
volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
|
|
volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
|
|
volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
|
|
|
|
/* response */
|
|
uint32_t *response; /**< pointer to buffer for executing command. */
|
|
uint32_t r1_card_status; /**< R1 response data */
|
|
uint32_t r3_ocr; /**< R3 response data */
|
|
uint32_t r4_resp; /**< R4 response data */
|
|
uint32_t r5_resp; /**< R5 response data */
|
|
|
|
uint32_t low_clock_mode_enable;
|
|
/**< True : clock mode is low. (MMC clock = Max26MHz) */
|
|
uint32_t reserved2;
|
|
uint32_t reserved3;
|
|
uint32_t reserved4;
|
|
|
|
/* CSD registers (4byte align) */
|
|
uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */
|
|
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
|
|
/* CID registers (4byte align) */
|
|
uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */
|
|
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
|
|
/* EXT CSD registers (8byte align) */
|
|
uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */
|
|
__attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
|
|
/* Response registers (4byte align) */
|
|
uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */
|
|
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
|
|
} st_mmc_base;
|
|
|
|
typedef int (*func) (void);
|
|
|
|
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
|
|
|
|
/* ************************** FUNCTION PROTOTYPES ************************** */
|
|
uint32_t emmc_get_csd_time(void);
|
|
|
|
#define MMC_DEBUG
|
|
/* ********************************* CODE ********************************** */
|
|
|
|
/* ******************************** END ************************************ */
|
|
#endif /* EMMC_STD_H */
|