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https://github.com/ARM-software/arm-trusted-firmware.git
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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
260 lines
9.8 KiB
C
260 lines
9.8 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file emmc_registers.h
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* @brief emmc boot driver is expecting this header file. HS-MMC module header file.
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*
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*/
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#ifndef EMMC_REGISTERS_H
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#define EMMC_REGISTERS_H
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/* ************************ HEADER (INCLUDE) SECTION *********************** */
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/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
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/* MMC channel select */
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#define MMC_CH0 (0U) /* SDHI2/MMC0 */
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#define MMC_CH1 (1U) /* SDHI3/MMC1 */
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#if RCAR_LSI == RCAR_E3
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#define USE_MMC_CH (MMC_CH1) /* R-Car E3 */
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#else /* RCAR_LSI == RCAR_E3 */
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#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
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#endif /* RCAR_LSI == RCAR_E3 */
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#define BIT0 (0x00000001U)
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#define BIT1 (0x00000002U)
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#define BIT2 (0x00000004U)
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#define BIT3 (0x00000008U)
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#define BIT4 (0x00000010U)
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#define BIT5 (0x00000020U)
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#define BIT6 (0x00000040U)
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#define BIT7 (0x00000080U)
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#define BIT8 (0x00000100U)
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#define BIT9 (0x00000200U)
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#define BIT10 (0x00000400U)
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#define BIT11 (0x00000800U)
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#define BIT12 (0x00001000U)
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#define BIT13 (0x00002000U)
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#define BIT14 (0x00004000U)
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#define BIT15 (0x00008000U)
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#define BIT16 (0x00010000U)
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#define BIT17 (0x00020000U)
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#define BIT18 (0x00040000U)
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#define BIT19 (0x00080000U)
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#define BIT20 (0x00100000U)
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#define BIT21 (0x00200000U)
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#define BIT22 (0x00400000U)
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#define BIT23 (0x00800000U)
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#define BIT24 (0x01000000U)
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#define BIT25 (0x02000000U)
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#define BIT26 (0x04000000U)
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#define BIT27 (0x08000000U)
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#define BIT28 (0x10000000U)
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#define BIT29 (0x20000000U)
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#define BIT30 (0x40000000U)
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#define BIT31 (0x80000000U)
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/** @brief Clock Pulse Generator (CPG) registers
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*/
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#define CPG_BASE (0xE6150000U)
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#define CPG_MSTPSR3 (CPG_BASE+0x0048U) /* Module stop status register 3 */
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#define CPG_SMSTPCR3 (CPG_BASE+0x013CU) /* System module stop control register 3 */
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#define CPG_SD2CKCR (CPG_BASE+0x0268U) /* SDHI2 clock frequency control register */
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#define CPG_SD3CKCR (CPG_BASE+0x026CU) /* SDHI3 clock frequency control register */
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#define CPG_CPGWPR (CPG_BASE+0x0900U) /* CPG Write Protect Register */
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#if USE_MMC_CH == MMC_CH0
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#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
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#else /* USE_MMC_CH == MMC_CH0 */
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#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
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#endif /* USE_MMC_CH == MMC_CH0 */
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/** Boot Status register
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*/
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#define MFISBTSTSR (0xE6260604U)
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#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
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/** brief eMMC registers
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*/
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#define MMC0_SD_BASE (0xEE140000U)
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#define MMC1_SD_BASE (0xEE160000U)
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#if USE_MMC_CH == MMC_CH0
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#define MMC_SD_BASE (MMC0_SD_BASE)
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#else /* USE_MMC_CH == MMC_CH0 */
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#define MMC_SD_BASE (MMC1_SD_BASE)
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#endif /* USE_MMC_CH == MMC_CH0 */
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#define SD_CMD (MMC_SD_BASE + 0x0000U)
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#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
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#define SD_ARG (MMC_SD_BASE + 0x0010U)
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#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
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#define SD_STOP (MMC_SD_BASE + 0x0020U)
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#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
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#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
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#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
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#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
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#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
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#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
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#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
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#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
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#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
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#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
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#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
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#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
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#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
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#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
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#define SD_SIZE (MMC_SD_BASE + 0x0098U)
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#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
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#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
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#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
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#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
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#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
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#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
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#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
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#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
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#define SOFT_RST (MMC_SD_BASE + 0x0380U)
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#define VERSION (MMC_SD_BASE + 0x0388U)
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#define HOST_MODE (MMC_SD_BASE + 0x0390U)
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#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
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#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
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#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
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#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
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#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
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#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
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#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
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#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
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/** @brief SD_INFO1 Registers
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*/
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#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
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#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
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#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
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#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
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#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
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#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
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#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
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#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
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#define SD_INFO1_INFO2 0x00000004UL /* Access end */
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#define SD_INFO1_INFO0 0x00000001UL /* Response end */
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/** @brief SD_INFO2 Registers
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*/
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#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
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#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
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#define SD_INFO2_SCLKDIVEN 0x00002000UL
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#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
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#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
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#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
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#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
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#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
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#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
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#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
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#define SD_INFO2_ERR2 0x00000004UL /* END Error */
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#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
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#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
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#define SD_INFO2_ALL_ERR 0x0000807FUL
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#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */
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/** @brief SOFT_RST
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*/
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#define SOFT_RST_SDRST 0x00000001UL
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/** @brief SD_CLK_CTRL
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*/
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#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
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#define SD_CLK_CTRL_SCLKEN 0x00000100UL
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#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
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#define SD_CLOCK_ENABLE 0x00000100UL
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#define SD_CLOCK_DISABLE 0x00000000UL
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#define SD_CLK_WRITE_MASK 0x000003FFUL
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#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
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/** @brief SD_OPTION
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*/
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#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
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/** @brief MMC Clock Frequency
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* 200MHz * 1/x = output clock
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*/
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#define MMC_CLK_OFF 0UL /* Clock output is disabled */
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#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
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#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
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#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */
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#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */
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#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
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#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
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#define MMC_FREQ_52MHZ 52000000UL
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#define MMC_FREQ_26MHZ 26000000UL
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#define MMC_FREQ_20MHZ 20000000UL
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/** @brief MMC Clock DIV
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*/
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#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
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#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
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#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
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#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
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#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
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#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
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#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
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#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
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#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
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#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
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#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
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#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
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/** @brief DM_CM_DTRAN_MODE
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*/
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#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
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#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
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#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
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/** @brief CC_EXT_MODE
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*/
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#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
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#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
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/** @brief DM_CM_INFO_MASK
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*/
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#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
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#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
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#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
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/** @brief DM_DTRAN_ADDR
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*/
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#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
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/** @brief DM_CM_DTRAN_CTRL
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*/
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#define DM_CM_DTRAN_CTRL_START 0x00000001UL
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/** @brief SYSC Registers
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*/
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#if USE_MMC_CH == MMC_CH0
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#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
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#else /* USE_MMC_CH == MMC_CH0 */
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#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
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#endif /* USE_MMC_CH == MMC_CH0 */
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/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
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/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
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/* ************************** FUNCTION PROTOTYPES ************************** */
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/* ********************************* CODE ********************************** */
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#endif /* EMMC_REGISTERS_H */
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/* ******************************** END ************************************ */
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