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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A3700_CONSOLE_H
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#define A3700_CONSOLE_H
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/* MVEBU UART Registers */
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#define UART_RX_REG 0x00
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#define UART_TX_REG 0x04
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#define UART_CTRL_REG 0x08
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#define UART_STATUS_REG 0x0c
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#define UART_BAUD_REG 0x10
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#define UART_POSSR_REG 0x14
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/* FIFO Control Register bits */
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#define UARTFCR_FIFOMD_16450 (0 << 6)
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#define UARTFCR_FIFOMD_16550 (1 << 6)
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#define UARTFCR_RXTRIG_1 (0 << 6)
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#define UARTFCR_RXTRIG_4 (1 << 6)
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#define UARTFCR_RXTRIG_8 (2 << 6)
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#define UARTFCR_RXTRIG_16 (3 << 6)
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#define UARTFCR_TXTRIG_1 (0 << 4)
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#define UARTFCR_TXTRIG_4 (1 << 4)
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#define UARTFCR_TXTRIG_8 (2 << 4)
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#define UARTFCR_TXTRIG_16 (3 << 4)
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#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
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#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
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#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
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#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
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/* Line Control Register bits */
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#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
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#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
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#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
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#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
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#define UARTLCR_PAR (1 << 3) /* Parity */
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#define UARTLCR_STOP (1 << 2) /* Stop Bit */
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#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
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#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
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#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
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#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
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/* Line Status Register bits */
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#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
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/* UART Control Register bits */
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#define UART_CTRL_RXFIFO_RESET (1 << 14)
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#define UART_CTRL_TXFIFO_RESET (1 << 15)
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#define UARTLSR_TXFIFOEMPTY (1 << 6)
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#endif /* A3700_CONSOLE_H */
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