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https://github.com/ARM-software/arm-trusted-firmware.git
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c3ce73be0b
In the comment in the ARM FPGA DT we promise a generous 100 MB initrd, but actually describe only a size of 20 MB. As initrds are the most common and easy userland option for the boards, let's increase the maximum size to the advertised 100 MB, to avoid unpacking errors when an initrd exceeds the current limit of 20 MB. Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
102 lines
2.5 KiB
Text
102 lines
2.5 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* Devicetree for the Arm Ltd. FPGA platform
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* Number and kind of CPU cores differs from image to image, so the
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* topology is auto-detected by BL31, and the /cpus node is created and
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* populated accordingly at runtime.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "ARM FPGA";
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compatible = "arm,fpga", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &dbg_uart;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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bootargs = "console=ttyAMA0,38400n8 earlycon";
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/* Allow to upload a generous 100MB initrd payload. */
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linux,initrd-start = <0x0 0x84000000>;
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linux,initrd-end = <0x0 0x8a400000>;
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};
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/* /cpus node will be added by BL31 at runtime. */
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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clock-frequency = <10000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* This node will be removed at runtime on cores without SPE. */
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>,
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<0x8 0x80000000 0x1 0x80000000>;
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};
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bus_refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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uartclk: baudclock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <10000000>;
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clock-output-names = "uartclk";
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};
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dbg_uart: serial@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x00001000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&bus_refclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0x0 0x00010000>, /* GICD */
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/* The GICR size will be adjusted at runtime to match the cores. */
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<0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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