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https://github.com/ARM-software/arm-trusted-firmware.git
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c3260f9b82
Previously exception handlers in BL3-1, X19-X29 were not saved and restored on every SMC/trap into EL3. Instead these registers were 'saved as needed' as a side effect of the A64 ABI used by the C compiler. That approach failed when world switching but was not visible with the TSP/TSPD code because the TSP is 64-bit, did not clobber these registers when running and did not support pre-emption by normal world interrupts. These scenarios showed that the values in these registers can be passed through a world switch, which broke the normal and trusted world assumptions about these registers being preserved. The Ideal solution saves and restores these registers when a world switch occurs - but that type of implementation is more complex. So this patch always saves and restores these registers on entry and exit of EL3. Fixes ARM-software/tf-issues#141 Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
164 lines
4.5 KiB
ArmAsm
164 lines
4.5 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cm_macros.S>
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#include <psci.h>
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.globl psci_aff_on_finish_entry
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.globl psci_aff_suspend_finish_entry
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.globl __psci_cpu_off
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.globl __psci_cpu_suspend
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/* -----------------------------------------------------
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* This cpu has been physically powered up. Depending
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* upon whether it was resumed from suspend or simply
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* turned on, call the common power on finisher with
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* the handlers (chosen depending upon original state).
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* For ease, the finisher is called with coherent
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* stacks. This allows the cluster/cpu finishers to
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* enter coherency and enable the mmu without running
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* into issues. We switch back to normal stacks once
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* all this is done.
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* -----------------------------------------------------
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*/
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func psci_aff_on_finish_entry
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adr x23, psci_afflvl_on_finishers
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b psci_aff_common_finish_entry
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psci_aff_suspend_finish_entry:
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adr x23, psci_afflvl_suspend_finishers
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psci_aff_common_finish_entry:
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adr x22, psci_afflvl_power_on_finish
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/* ---------------------------------------------
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* Exceptions should not occur at this point.
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* Set VBAR in order to handle and report any
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* that do occur
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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*/
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msr spsel, #0
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isb
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bl read_mpidr
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mov x19, x0
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bl platform_set_coherent_stack
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/* ---------------------------------------------
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* Call the finishers starting from affinity
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* level 0.
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* ---------------------------------------------
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*/
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mov x0, x19
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bl get_power_on_target_afflvl
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cmp x0, xzr
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b.lt _panic
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mov x3, x23
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mov x2, x0
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mov x0, x19
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mov x1, #MPIDR_AFFLVL0
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blr x22
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/* --------------------------------------------
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* Give ourselves a stack allocated in Normal
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* -IS-WBWA memory
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* --------------------------------------------
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*/
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mov x0, x19
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bl platform_set_stack
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b el3_exit
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_panic:
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b _panic
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/* -----------------------------------------------------
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* The following two stubs give the calling cpu a
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* coherent stack to allow flushing of caches without
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* suffering from stack coherency issues
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* -----------------------------------------------------
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*/
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func __psci_cpu_off
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func_prologue
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sub sp, sp, #0x10
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stp x19, x20, [sp, #0]
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mov x19, sp
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bl read_mpidr
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bl platform_set_coherent_stack
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bl psci_cpu_off
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mov x1, #PSCI_E_SUCCESS
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cmp x0, x1
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b.eq final_wfi
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mov sp, x19
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ldp x19, x20, [sp,#0]
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add sp, sp, #0x10
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func_epilogue
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ret
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func __psci_cpu_suspend
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func_prologue
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sub sp, sp, #0x20
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stp x19, x20, [sp, #0]
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stp x21, x22, [sp, #0x10]
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mov x19, sp
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mov x20, x0
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mov x21, x1
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mov x22, x2
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bl read_mpidr
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bl platform_set_coherent_stack
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mov x0, x20
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mov x1, x21
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mov x2, x22
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bl psci_cpu_suspend
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mov x1, #PSCI_E_SUCCESS
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cmp x0, x1
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b.eq final_wfi
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mov sp, x19
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ldp x21, x22, [sp,#0x10]
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ldp x19, x20, [sp,#0]
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add sp, sp, #0x20
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func_epilogue
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ret
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func final_wfi
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dsb sy
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wfi
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wfi_spill:
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b wfi_spill
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