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https://github.com/ARM-software/arm-trusted-firmware.git
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b7c6529c41
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <utils_def.h>
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#include "../hikey960_def.h"
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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/*
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* Generic platform constants
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*/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x1000
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* UFS RPMB and UFS User Data */
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#define MAX_IO_BLOCK_DEVICES U(2)
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/*
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* Platform memory map related constants
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*/
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/*
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* BL1 specific defines.
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*/
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#define BL1_RO_BASE (0x1AC00000)
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#define BL1_RO_LIMIT (BL1_RO_BASE + 0x20000)
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#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */
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#define BL1_RW_SIZE (0x00188000)
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#define BL1_RW_LIMIT (0x1B000000)
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/*
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* BL2 specific defines.
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*/
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#define BL2_BASE (0x1AC00000)
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#define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
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/*
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* BL31 specific defines.
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*/
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#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
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#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM.
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*/
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
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#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#endif
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#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
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#error "SRAM storage of TSP payload is currently unsupported"
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#else
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#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
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#define NS_BL1U_SIZE (0x00100000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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#define HIKEY960_NS_IMAGE_OFFSET (0x1AC28000) /* offset in l-loader */
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#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
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#define SCP_BL2_BASE (0x89C80000)
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#define SCP_BL2_SIZE (0x00040000)
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/*
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* Platform specific page table and MMU setup constants
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*/
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
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#define MAX_XLAT_TABLES 3
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#endif
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#ifdef IMAGE_BL2
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#ifdef SPD_opteed
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#define MAX_XLAT_TABLES 4
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#else
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#define MAX_XLAT_TABLES 3
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#endif
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#endif
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#define MAX_MMAP_REGIONS 16
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/*
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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