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e25fc9df25
Neoverse-V3 erratum 3701767 that applies to r0p0, r0p1, r0p2 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2891958/latest/ Change-Id: I5be0de881f408a9e82a07b8459d79490e9065f94 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V3_H
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#define NEOVERSE_V3_H
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#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
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#define NEOVERSE_V3_MIDR U(0x410FD840)
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/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register 6 specific definitions
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******************************************************************************/
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#define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1
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#ifndef __ASSEMBLER__
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long check_erratum_neoverse_v3_3701767(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* NEOVERSE_V3_H */
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