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adea6e52a7
Neoverse-N2 erratum 3701773 that applies to r0p0, r0p1, r0p2 and r0p3 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest/ Change-Id: If95bd67363228c8083724b31f630636fb27f3b61 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
76 lines
3.4 KiB
C
76 lines
3.4 KiB
C
/*
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* Copyright (c) 2020-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_N2_H
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#define NEOVERSE_N2_H
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/* Neoverse N2 ID register for revision r0p0 */
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#define NEOVERSE_N2_MIDR U(0x410FD490)
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/* Neoverse N2 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_N2_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Power control register
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******************************************************************************/
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#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
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#define CPUECTLR2_EL1_TXREQ_LSB U(0)
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#define CPUECTLR2_EL1_TXREQ_WIDTH U(3)
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#ifndef __ASSEMBLER__
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long check_erratum_neoverse_n2_3701773(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* NEOVERSE_N2_H */
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