mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
463b5b4a46
Cortex-A710 erratum 3701772 that applies to all revisions <= r2p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I997c9cfaa75321f22b4f690c4d3f234c0b51c670 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
74 lines
3.3 KiB
C
74 lines
3.3 KiB
C
/*
|
|
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef CORTEX_A710_H
|
|
#define CORTEX_A710_H
|
|
|
|
#define CORTEX_A710_MIDR U(0x410FD470)
|
|
|
|
/* Cortex-A710 loop count for CVE-2022-23960 mitigation */
|
|
#define CORTEX_A710_BHB_LOOP_COUNT U(32)
|
|
|
|
/*******************************************************************************
|
|
* CPU Extended Control register specific definitions
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
|
|
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
|
|
|
/*******************************************************************************
|
|
* CPU Power Control register specific definitions
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
|
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
|
#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register 2 specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
|
|
#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
|
#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register 3 specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR3_EL1 S3_0_C15_C1_2
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register 5 specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
|
|
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
|
#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
|
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
|
|
#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
|
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
|
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
|
|
|
/*******************************************************************************
|
|
* CPU Selected Instruction Private register specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0
|
|
#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1
|
|
#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2
|
|
#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3
|
|
|
|
#ifndef __ASSEMBLER__
|
|
long check_erratum_cortex_a710_3701772(long cpu_rev);
|
|
#endif /* __ASSEMBLER__ */
|
|
|
|
#endif /* CORTEX_A710_H */
|