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https://github.com/ARM-software/arm-trusted-firmware.git
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bf223c7937
Currently used stream id 0x200 gives below fault, [ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000 [ 9.547393][ C0] raw fault status: 0x400D02C0 [ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0 [ 9.547393][ C0] access type 0x2: READ As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it. Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95 Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com> Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
94 lines
1.9 KiB
Text
94 lines
1.9 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define MHU_TX_ADDR 46240000 /* hex */
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#define MHU_RX_ADDR 46250000 /* hex */
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#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
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#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
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#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
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#define RSE_MHU_TX_ADDR 49020000 /* hex */
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#define RSE_MHU_RX_ADDR 49030000 /* hex */
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#define ETHERNET_ADDR 64000000
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#define ETHERNET_INT 799
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#define SYS_REGS_ADDR 60080000
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#define MMC_ADDR 600b0000
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#define MMC_INT_0 778
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#define MMC_INT_1 779
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#define RTC_ADDR 600a0000
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#define RTC_INT 777
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#define KMI_0_ADDR 60100000
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#define KMI_0_INT 784
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#define KMI_1_ADDR 60110000
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#define KMI_1_INT 785
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#define VIRTIO_BLOCK_ADDR 60020000
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#define VIRTIO_BLOCK_INT 769
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc3-4-base.dtsi"
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/ {
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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dp0: display@DPU_ADDR {
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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};
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gpu: gpu@2d000000 {
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "IRQAW";
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iommus = <&smmu_700 0x0>;
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};
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dsu-pmu {
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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cs-pmu@4 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>;
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};
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cs-pmu@5 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>;
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};
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cs-pmu@6 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>;
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};
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cs-pmu@7 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
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};
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};
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