mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
beb625f90b
Add the support of the TRUSTED_BOARD_BOOT to authenticate the loaded FIP using platform CoT management. It adds TBB platform definition, redefining the standard image ID in order to decrease requested size in BL2 binary. Authentication will use mbedTLS library for parsing certificate configured with a platform configuration. Change-Id: I9da66b915c5e9e9293fccfce92bef2434da1e430 Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
138 lines
4.1 KiB
C
138 lines
4.1 KiB
C
/*
|
|
* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef STM32MP1_FIP_DEF_H
|
|
#define STM32MP1_FIP_DEF_H
|
|
|
|
#if STM32MP15_OPTEE_RSV_SHM
|
|
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
|
|
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
|
|
#else
|
|
#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
|
|
#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
|
|
#endif
|
|
|
|
#if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP
|
|
#if STM32MP15
|
|
#define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */
|
|
#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
|
|
#endif /* STM32MP15 */
|
|
#else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */
|
|
#if STM32MP13
|
|
#if BL2_IN_XIP_MEM
|
|
#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */
|
|
#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */
|
|
#else
|
|
/* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */
|
|
#define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */
|
|
/* with 20KB for DTB, SYSRAM is full */
|
|
#endif
|
|
#endif /* STM32MP13 */
|
|
#if STM32MP15
|
|
#define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */
|
|
#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
|
|
#endif /* STM32MP15 */
|
|
#endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */
|
|
|
|
#if STM32MP13
|
|
#if TRUSTED_BOARD_BOOT
|
|
#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
|
|
#else /* TRUSTED_BOARD_BOOT */
|
|
#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */
|
|
#endif /* TRUSTED_BOARD_BOOT */
|
|
#endif /* STM32MP13 */
|
|
#if STM32MP15
|
|
#define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */
|
|
#endif /* STM32MP15 */
|
|
#define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */
|
|
#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
|
|
#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
|
|
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
|
|
|
|
#if STM32MP13
|
|
#define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \
|
|
STM32MP_BL2_DTB_SIZE)
|
|
#endif /* STM32MP13 */
|
|
#if STM32MP15
|
|
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
|
|
STM32MP_SEC_SYSRAM_SIZE - \
|
|
STM32MP_BL2_SIZE)
|
|
#endif /* STM32MP15 */
|
|
|
|
#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
|
|
|
|
#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
|
|
STM32MP_BL2_RO_SIZE)
|
|
|
|
#if STM32MP13
|
|
#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
|
|
STM32MP_SYSRAM_SIZE - \
|
|
STM32MP_BL2_RW_BASE)
|
|
|
|
#define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE
|
|
#endif /* STM32MP13 */
|
|
#if STM32MP15
|
|
#define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \
|
|
STM32MP_SEC_SYSRAM_SIZE - \
|
|
STM32MP_BL2_RW_BASE)
|
|
|
|
#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
|
|
STM32MP_BL2_DTB_SIZE)
|
|
#endif /* STM32MP15 */
|
|
|
|
#define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE
|
|
|
|
#define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \
|
|
STM32MP_BL32_DTB_SIZE)
|
|
|
|
|
|
#if defined(IMAGE_BL2)
|
|
#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
|
|
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
|
|
#endif
|
|
#if defined(IMAGE_BL32)
|
|
#define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE
|
|
#define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE
|
|
#endif
|
|
|
|
#ifdef AARCH32_SP_OPTEE
|
|
#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
|
|
|
|
#define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \
|
|
STM32MP_OPTEE_BASE)
|
|
#endif
|
|
|
|
#if STM32MP13
|
|
#define STM32MP_FW_CONFIG_BASE SRAM3_BASE
|
|
#endif /* STM32MP13 */
|
|
#if STM32MP15
|
|
#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
|
|
STM32MP_SYSRAM_SIZE - \
|
|
PAGE_SIZE)
|
|
#endif /* STM32MP15 */
|
|
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
|
|
STM32MP_BL33_MAX_SIZE)
|
|
|
|
/*
|
|
* MAX_MMAP_REGIONS is usually:
|
|
* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
|
|
*/
|
|
#if defined(IMAGE_BL32)
|
|
#define MAX_MMAP_REGIONS 10
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
* STM32MP1 RAW partition offset for devices without GPT
|
|
******************************************************************************/
|
|
#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
|
|
#ifndef STM32MP_NOR_FIP_OFFSET
|
|
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
|
|
#endif
|
|
#ifndef STM32MP_NAND_FIP_OFFSET
|
|
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
|
|
#endif
|
|
|
|
#endif /* STM32MP1_FIP_DEF_H */
|