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This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
164 lines
6 KiB
C
164 lines
6 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <gicv2.h>
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#include <platform_def.h>
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#include "qemu_private.h"
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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* limit of the BL3-1 image. These addresses are used by the MMU setup code and
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* therefore they must be page-aligned. It is the responsibility of the linker
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* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL3-1 from BL2.
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*/
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Perform any BL3-1 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* Initialize the console to provide early debug support */
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console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
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PLAT_QEMU_CONSOLE_BAUDRATE);
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* In debug builds, we pass a special value in 'plat_params_from_bl2'
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* to verify platform parameters from BL2 to BL3-1.
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* In release builds, it's not used.
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*/
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assert(((unsigned long long)plat_params_from_bl2) ==
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QEMU_BL31_PLAT_PARAM_VAL);
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/*
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* Copy BL3-2 (if populated by BL2) and BL3-3 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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if (from_bl2->bl32_ep_info)
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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}
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void bl31_plat_arch_setup(void)
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{
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qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
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BL31_RO_BASE, BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT);
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}
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static const unsigned int irq_sec_array[] = {
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QEMU_IRQ_SEC_SGI_0,
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QEMU_IRQ_SEC_SGI_1,
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QEMU_IRQ_SEC_SGI_2,
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QEMU_IRQ_SEC_SGI_3,
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QEMU_IRQ_SEC_SGI_4,
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QEMU_IRQ_SEC_SGI_5,
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QEMU_IRQ_SEC_SGI_6,
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QEMU_IRQ_SEC_SGI_7,
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};
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static const struct gicv2_driver_data plat_gicv2_driver_data = {
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.gicd_base = GICD_BASE,
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.gicc_base = GICC_BASE,
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.g0_interrupt_num = ARRAY_SIZE(irq_sec_array),
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.g0_interrupt_array = irq_sec_array,
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};
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void bl31_platform_setup(void)
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{
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/* Initialize the gic cpu and distributor interfaces */
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gicv2_driver_init(&plat_gicv2_driver_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image
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* for the security state specified. BL3-3 corresponds to the non-secure
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* image type while BL3-2 corresponds to the secure image type. A NULL
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* pointer is returned if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(sec_state_is_valid(type));
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next_image_info = (type == NON_SECURE)
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? &bl33_image_ep_info : &bl32_image_ep_info;
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/*
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* None of the images on the ARM development platforms can have 0x0
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* as the entrypoint
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*/
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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