mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-05-01 16:13:16 +00:00
877cf3ff12
This patch adds AArch32 support for FVP and implements common platform APIs like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for AArch32. Only Multi Processor(MP) implementations of these functions are considered in this patch. The ARM Standard platform layer helpers are implemented for AArch32 and the common makefiles are modified to cater for both AArch64 and AArch32 builds. Compatibility with the deprecated platform API is not supported for AArch32. Change-Id: Iad228400613eec91abf731b49e21a15bcf2833ea
117 lines
4.6 KiB
C
117 lines
4.6 KiB
C
/*
|
|
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
*
|
|
* Redistributions of source code must retain the above copyright notice, this
|
|
* list of conditions and the following disclaimer.
|
|
*
|
|
* Redistributions in binary form must reproduce the above copyright notice,
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
* and/or other materials provided with the distribution.
|
|
*
|
|
* Neither the name of ARM nor the names of its contributors may be used
|
|
* to endorse or promote products derived from this software without specific
|
|
* prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#include <arm_def.h>
|
|
#include <gicv3.h>
|
|
#include <plat_arm.h>
|
|
#include <platform.h>
|
|
#include <platform_def.h>
|
|
|
|
/******************************************************************************
|
|
* The following functions are defined as weak to allow a platform to override
|
|
* the way the GICv3 driver is initialised and used.
|
|
*****************************************************************************/
|
|
#pragma weak plat_arm_gic_driver_init
|
|
#pragma weak plat_arm_gic_init
|
|
#pragma weak plat_arm_gic_cpuif_enable
|
|
#pragma weak plat_arm_gic_cpuif_disable
|
|
#pragma weak plat_arm_gic_pcpu_init
|
|
|
|
/* The GICv3 driver only needs to be initialized in EL3 */
|
|
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
|
|
|
/* Array of Group1 secure interrupts to be configured by the gic driver */
|
|
static const unsigned int g1s_interrupt_array[] = {
|
|
PLAT_ARM_G1S_IRQS
|
|
};
|
|
|
|
/* Array of Group0 interrupts to be configured by the gic driver */
|
|
static const unsigned int g0_interrupt_array[] = {
|
|
PLAT_ARM_G0_IRQS
|
|
};
|
|
|
|
const gicv3_driver_data_t arm_gic_data = {
|
|
.gicd_base = PLAT_ARM_GICD_BASE,
|
|
.gicr_base = PLAT_ARM_GICR_BASE,
|
|
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
|
|
.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
|
|
.g0_interrupt_array = g0_interrupt_array,
|
|
.g1s_interrupt_array = g1s_interrupt_array,
|
|
.rdistif_num = PLATFORM_CORE_COUNT,
|
|
.rdistif_base_addrs = rdistif_base_addrs,
|
|
.mpidr_to_core_pos = plat_arm_calc_core_pos
|
|
};
|
|
|
|
void plat_arm_gic_driver_init(void)
|
|
{
|
|
/*
|
|
* The GICv3 driver is initialized in EL3 and does not need
|
|
* to be initialized again in SEL1. This is because the S-EL1
|
|
* can use GIC system registers to manage interrupts and does
|
|
* not need GIC interface base addresses to be configured.
|
|
*/
|
|
#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32)
|
|
gicv3_driver_init(&arm_gic_data);
|
|
#endif
|
|
}
|
|
|
|
/******************************************************************************
|
|
* ARM common helper to initialize the GIC. Only invoked by BL31
|
|
*****************************************************************************/
|
|
void plat_arm_gic_init(void)
|
|
{
|
|
gicv3_distif_init();
|
|
gicv3_rdistif_init(plat_my_core_pos());
|
|
gicv3_cpuif_enable(plat_my_core_pos());
|
|
}
|
|
|
|
/******************************************************************************
|
|
* ARM common helper to enable the GIC CPU interface
|
|
*****************************************************************************/
|
|
void plat_arm_gic_cpuif_enable(void)
|
|
{
|
|
gicv3_cpuif_enable(plat_my_core_pos());
|
|
}
|
|
|
|
/******************************************************************************
|
|
* ARM common helper to disable the GIC CPU interface
|
|
*****************************************************************************/
|
|
void plat_arm_gic_cpuif_disable(void)
|
|
{
|
|
gicv3_cpuif_disable(plat_my_core_pos());
|
|
}
|
|
|
|
/******************************************************************************
|
|
* ARM common helper to initialize the per-cpu redistributor interface in GICv3
|
|
*****************************************************************************/
|
|
void plat_arm_gic_pcpu_init(void)
|
|
{
|
|
gicv3_rdistif_init(plat_my_core_pos());
|
|
}
|